?? juchi_address.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity juchi_address is
port(
clk:in std_logic;
addin:in std_logic_vector(9 downto 0);
addout:out std_logic_vector(7 downto 0));
end;
architecture delta of juchi_address is
signal count:std_logic_vector(7 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
count<=count+1;
addout(7 downto 0)<=addin(7 downto 0);
end if ;
end process;
end;
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