library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--MCU與FPGA通信采用總線方式,其中,EN為使能端
entity keyscan is 
port(clk:in std_logic;
     mcuaddr:in std_logic_vector(1 downto 0);--地址信號
                                             --00為清零,01為頻率字,10為相位字,11為選擇波形輸出
     EN:in std_logic;--使能信號,當MCU給與下降沿時,FPGA動作
     clear:out std_logic;
     sel_wave:out std_logic_vector(1 downto 0);
     fcw,pcw:out std_logic_vector(7 downto 0));--數(shù)據(jù)送至MCU內(nèi)部
end;
architecture beh of keyscan is
signal tmp_fcw,tmp_pcw:std_logic_vector(7 downto 0);
signal tmp_sel:std_logic_vector(1 downto 0);
signal flag:std_logic;
begin
 
      process(clk,en,mcuaddr)--根據(jù)MCU給出的地址,給MCU送相應的數(shù)據(jù)
       begin
        if rising_edge(clk) then
         clear<='1';
         if en='0' then
          if flag='0' then
          case mcuaddr is
             when "00"=>clear<='0';tmp_fcw<=(others=>'0');tmp_pcw<=(others=>'0');tmp_sel<="00";
             when "01"=>clear<='0';tmp_fcw<=tmp_fcw+1;
             when "10"=>clear<='0';tmp_pcw<=tmp_pcw+1;
             when "11"=>tmp_sel<=tmp_sel+1;clear<='0';tmp_fcw<=(others=>'0');tmp_pcw<=(others=>'0');
             when others=>null;
          end case;
          flag<='1';
        end if;
      else flag<='0';
      end if;
     end if;
     end process;
fcw<=tmp_fcw;
pcw<=tmp_pcw;
sel_wave<=tmp_sel;
end;