?? fangbo.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fangbo is
port(clk:in std_logic;
data_out:out std_logic_vector(7 downto 0));
end;
architecture fangbo of fangbo is
signal counter:integer range 0 to 511;
begin
process(clk)
begin
if rising_edge(clk) then
counter<=counter+1;
end if;
end process;
process(counter)
begin
if counter<256 then
data_out<=(others=>'0');
else
data_out<=(others=>'1');
end if;
end process;
end;
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