Version 6.0 Build 178 04/27/2006 SJ Full Version
35
1731
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
dds
# storage
db|dds.(0).cnf
db|dds.(0).cnf
# case_insensitive
# source_file
dds.bdf
ff4e3839a61ac72d4611ce1a67577c0
24
# hierarchies {
|
}
# end
# entity
selectwave
# storage
db|dds.(1).cnf
db|dds.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
selectwave.vhd
d43e197a9435a4ef9fa4ecbc22e649
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
selectwave:inst11
}
# end
# entity
frediv
# storage
db|dds.(2).cnf
db|dds.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
frediv.vhd
4f1fa0c2dde83881e3934cd6f8e7598
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
n
4
PARAMETER_UNKNOWN
USR
}
# hierarchies {
frediv:inst14
}
# end
# entity
frediv
# storage
db|dds.(3).cnf
db|dds.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
frediv.vhd
4f1fa0c2dde83881e3934cd6f8e7598
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
n
9
PARAMETER_UNKNOWN
USR
}
# hierarchies {
frediv:inst13
}
# end
# entity
delta
# storage
db|dds.(4).cnf
db|dds.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
delta.vhd
c255cecb3dc756d829f398dfd81796
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
delta:inst6
delta:inst9
}
# end
# entity
altsyncram
# storage
db|dds.(5).cnf
db|dds.(5).cnf
# case_insensitive
# source_file
f:|altera|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
./romdata/delta.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_hq31
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
f:|altera|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
f:|altera|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
f:|altera|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
f:|altera|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
f:|altera|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
f:|altera|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
f:|altera|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
f:|altera|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
f:|altera|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
f:|altera|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
delta:inst6|altsyncram:altsyncram_component
delta:inst9|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_hq31
# storage
db|dds.(6).cnf
db|dds.(6).cnf
# case_insensitive
# source_file
db|altsyncram_hq31.tdf
3cfce2bb5c87154136c1bcf4f1aa5ffb
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
.|romdata|delta.mif
b2abea4387dfa8ea5e2d4fda7e11a2fc
}
# hierarchies {
delta:inst6|altsyncram:altsyncram_component|altsyncram_hq31:auto_generated
delta:inst9|altsyncram:altsyncram_component|altsyncram_hq31:auto_generated
}
# end
# entity
delta_address
# storage
db|dds.(7).cnf
db|dds.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
delta_address.vhd
b52acda7c6883634213529f3214ab990
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
delta_address:inst7
}
# end
# entity
add_pcw
# storage
db|dds.(8).cnf
db|dds.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
add_pcw.vhd
5d62b9b6545a43e2d415f7613503f
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
add_pcw:inst1
}
# end
# entity
add_fcw
# storage
db|dds.(9).cnf
db|dds.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
add_fcw.vhd
737f90981dbcb720bff7c65ee9eee
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
add_fcw:inst
}
# end
# entity
fangbo
# storage
db|dds.(10).cnf
db|dds.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fangbo.vhd
7098648fdc7fa0b2df1431a22642c6c
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
fangbo:inst10
}
# end
# entity
juchi_address
# storage
db|dds.(11).cnf
db|dds.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
juchi_address.vhd
ee5176e9f3fed2a83659d1b2f0a7fa73
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
juchi_address:inst8
}
# end
# entity
sin_out
# storage
db|dds.(12).cnf
db|dds.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
sin_out.vhd
84f64f57d767852a9f163fdc7b79f8c7
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
sin_out:inst4
}
# end
# entity
sin_add
# storage
db|dds.(13).cnf
db|dds.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
sin_add.vhd
f07005a90cef95c6bdc8895933d8d6
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
sin_add:inst2
}
# end
# entity
sinrom
# storage
db|dds.(14).cnf
db|dds.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
sinrom.vhd
5791c992d14b689cdaee8683bac09cfc
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
sinrom:inst3
}
# end
# entity
altsyncram
# storage
db|dds.(15).cnf
db|dds.(15).cnf
# case_insensitive
# source_file
f:|altera|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
./romdata/sin.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_hk31
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
f:|altera|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
f:|altera|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
f:|altera|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
f:|altera|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
f:|altera|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
f:|altera|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
f:|altera|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
f:|altera|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
f:|altera|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
f:|altera|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
sinrom:inst3|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_hk31
# storage
db|dds.(16).cnf
db|dds.(16).cnf
# case_insensitive
# source_file
db|altsyncram_hk31.tdf
7168bb40512c77ee43705ca0aaa0133
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
.|romdata|sin.mif
4d6b9de8f52daf1cf3ec2251649b3d7
}
# hierarchies {
sinrom:inst3|altsyncram:altsyncram_component|altsyncram_hk31:auto_generated
}
# end
# entity
sld_signaltap
# storage
db|dds.(17).cnf
db|dds.(17).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
f:|altera|libraries|megafunctions|sld_signaltap.vhd
bafecb7d1122d6345cc8e1bd9a2a4bb5
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
536899072
PARAMETER_UNKNOWN
USR
sld_ip_version
4
PARAMETER_DEC
DEF
sld_ip_minor_version
0
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC
DEF
sld_data_bits
40
PARAMETER_UNKNOWN
USR
sld_trigger_bits
40
PARAMETER_UNKNOWN
USR
sld_data_bit_cntr_bits
6
PARAMETER_UNKNOWN
USR
sld_node_crc_bits
32
PARAMETER_DEC
DEF
sld_node_crc_hiword
44160
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
17583
PARAMETER_UNKNOWN
USR
sld_incremental_routing
0
PARAMETER_DEC
DEF
sld_sample_depth
1024
PARAMETER_UNKNOWN
USR
sld_mem_address_bits
10
PARAMETER_UNKNOWN
USR
sld_ram_block_type
AUTO
PARAMETER_STRING
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_2
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_3
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_4
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_5
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_6
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_7
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_8
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_9
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
139
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
}
# end
# entity
sld_ela_control
# storage
db|dds.(18).cnf
db|dds.(18).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
f:|altera|libraries|megafunctions|sld_ela_control.vhd
50f992f5a51ab387a478321569ab2eee
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
4
PARAMETER_DEC
USR
ip_minor_version
0
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
trigger_input_width
40
PARAMETER_DEC
USR
trigger_level
1
PARAMETER_DEC
USR
trigger_in_enabled
0
PARAMETER_DEC
USR
enable_clk_edge_def
0
PARAMETER_DEC
USR
enable_async_glitch
0
PARAMETER_DEC
USR
enable_sync_normal
1
PARAMETER_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_DEC
USR
trigger_level_pipeline
1
PARAMETER_DEC
USR
ela_status_bits
4
PARAMETER_DEC
USR
mem_address_bits
10
PARAMETER_DEC
USR
sample_depth
1024
PARAMETER_DEC
USR
inversion_mask_length
139
PARAMETER_DEC
USR
inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_BIN
USR
power_up_trigger
0
PARAMETER_DEC
USR
 constraint(acq_trigger_in)
39 downto 0
PARAMETER_STRING
USR
 constraint(status)
3 downto 0
PARAMETER_STRING
USR
}
# end
# entity
lpm_shiftreg
# storage
db|dds.(19).cnf
db|dds.(19).cnf
# case_insensitive
# source_file
f:|altera|libraries|megafunctions|lpm_shiftreg.tdf
5c3a6ccfa9758137252ac34dcc2420
6
# user_parameter {
LPM_WIDTH
19
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
shiftout
-1
3
shiftin
-1
3
q9
-1
3
q8
-1
3