; p30F4011.inc  Standard Include/Header File, Version 5
; (c) Copyright 2005 Microchip Technology, All rights reserved

.NOLIST

;******************************************************************************
;
; Important:
; ==========
; The processor must be selected before this file is included. The processor
; may  be selected in the following ways:
;
;       1. Command line switch:
;               C:\> AS -p30F4011
;       2. Placing a ".equ" directive before the ".include":
;               .equ __30F4011, 1
;               .include "p30F4011.inc"
;       3. Setting the processor in the MPLAB Project Dialog
;
; Notes:
; =========================
; 1. This include file defines useful bits of information for the
;    PIC30Fxxxx Family of Digital Signal Controllers (dsPIC).
; 2. The register and bit names used in this file are taken to match the
;    PIC30Fxxxx data sheets as closely as possible.
; 3. This file does not map special function register (SFR) names used in the
;    datasheet to memory locations in the PIC30Fxxxx device. The address
;    mapping for SFR names is done in the device linker script only.
; 4. It does however, provide names for the lower(even address) and
;    higher(odd address) bytes of a special function register. For e.g.,
;    the TMR2 register is 16 bits long and its memory address is provided in
;    the device linker script. This SFR can be alternately accessed as two
;    separate bytes, TMR2L and TMR2H.In such a case, TMR2L maps to the lower
;    byte and TMR2H maps to the higher byte. This mapping is performed in this
;    include file.
; 5. This file maps bit names used in the datasheet to bit offsets/positions
;    in a word [0x000F(15) for the MS bit down to 0x0000(0) for the LS bit].
; 6. SFR bit definitions are listed in the ascending order of SFR memory
;    addresses and are grouped based on the module they belong to. For e.g.,the
;    Core SFR  bits are grouped separately from the Interrupt Controller SFR
;    bits or the  General Purpose Timer SFR bits.
;
; File Structure/Organization:
; ============================
; The sections in this file are organized as shown below:
;       1. Core section
;          a. Byte High and Byte Low definitions for SFRs in the section
;          b. Bit Position Definitions for some SFRS in the section
;       2. Interrupt section
;          a. Byte High and Byte Low definitions for SFRs in the section
;          b. Bit Position Definitions for some SFRS in the section
;       :
;       :
;       13. Peripheral x section
;          a. Byte High and Byte Low definitions for SFRs in the section
;          b. Bit Position Definitions for some SFRS in the section
;       :
;       :
;       N. Useful constants that ease assembly-level programming
;       N+1. Configuration Fuses and Macros
;
; Revision History:
; =================
; --------------------------------------------------------------------------
; Rev:   Date:        Details:                                      Who:
; --------------------------------------------------------------------------
; 1.0   27 Nov 2001   Device-specific .inc files from superset      H Vasuki
; 1.1   13 Dec 2001   Added PMD, Changed SPI, UART, ADC + changes      -do-
; 1.2   14 Dec 2001   Modified CORCON bits to reflect Rev C Core       -do-
; 1.3   20 Feb 2002   PMD, CORCON, A/D, RCON, INTCONx, NVMCON          -do-
; 1.4   18 Mar 2002   Renumbered bits for extended support to
;                     Bit-instructions+changes to configuration        -do-
;                     and QEI sections
; 1.5   12 Apr 2002   MCPWM and CAN updates + 1 SPI change             -do-
; 1.6   23 Apr 2002   Reinserted SFR byte (high and low) defines       -do-
; 1.7   06 May 2002   Changed SZ bit to Z, removed SIZESEL1            -do-
; 1.8   13 May 2002   Added PROGOP bits, Added DL2 and moved EDT       -do-
; 1.9   13 May 2002   Added Config Fuse bits and e.g.s in FPORBOR      -do-
; 2.0   31 May 2002   Added DISI bit                                   -do-
; 2.1   13 Aug 2002   Changed I2C interrupt bit to match Datasheet     -do-
; 2.2   23 Aug 2002   Removed ADSTBY bit                               -do-
; 2.3   17 Sep 2002   Added TWRI bit / Removed OFFCAL bit              -do-
; 2.3.1 28 Oct 2002   Changed UPDN_CNT bit to UPDN_SRC                 -do-
; 2.3.2 02 Dec 2002   BTLMODE->SEG2PHTS, SJWS->SJW + Added CANCKS      -do-
; 2.4   02 Dec 2002   Updated Config Macro                             -do-
; 2.5   22 Jan 2003   Corrected ADDRERR bit name                       -do-
; 2.6   27 Jan 2003   Corrected FWDT Fuse Definition                   -do-
; 2.7   07 Mar 2003   Added the descriptive .error directive           -do-
; 2.8   10 Apr 2003   Added Miscellaneous Rev A2 device files          -do-
; 2.9   01 May 2003   This is the first release of Rev B Si files      -do-
;                     Both Rev A2 and Rev B Si files will be
;                     maintained until Rev B Si is available.
;                     Initial changes in Rev B Si include CAN, QEI
;                     and CORCON
; 3.0   02 May 2003   Corrected CAN bit TXB0(zero) to TXBO('o')        -do-
; 3.1   02 June 2003  Added CANCAP bit in CiCTRL                       -do-
; 3.2   23 Jun 2003   Correcetd CANCAP/Changed CONV to DONE            -do-
; 3.3   05 Sept 2003  Added TUNx bits in OSCCON for MSS1 Rev B Si      -do-
; 3.4   17 Sept 2003  Added IMVx bits in DFLTCON/Removed INDOUTx       -do-
; 3.5   12 Nov  2003  Added extra NOLIST directive for enhancing LST   -do-
; 3.6   25 Nov  2003  Renamed TUN4-TUN1 to TUN3 to TUN0                -do-
; 3.61  02 Apr  2004  Added CN17 and CN18 bits to CN 2 SFRs            -do-
; 3.7   08 Apr 2004   Enhanced Config macro examples for FOSC fuse     -do-
; 3.8   25 Oct  2004  Added "A" devices, OSCTUNL and changed ADCBUF    -do-
; 3.9   23 Jan 2005   Changed Config Macro for C30 v1.30 compliance    -do-
; 3.9a  23 Jan 2005   Removed LVD bits for Motor Ctrl family devices   -do-
; 4.0   01 Apr 2005   Global change "EC_IO" to "ECIO"/Fixed "__FOSC"   -do-
;                     Global change "ERC_IO" to "ERCIO"
; 4.0a  28 Jun 2005   Changed all fuse & config macros to match SIBv2  -do-
; 4.1   28 Jun 2005   Added IUE bit in PWMCON2                         -do-
; 5.0   07 Nov 2005   Removed SECUREFLT bit                            -do-
; --------------------------------------------------------------------------
;
;******************************************************************************


;==============================================================================
;
; Verify Processor Type
;
;==============================================================================

.IFNDEF __30F4011
   .error "Include file does not match processor setting."
.ENDIF
.NOLIST

;==============================================================================
;
; 1. Core Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 1a. SFR Definitions
;------------------------------------------------------------------------------
         .equiv WREG0L, _WREG0
         .equiv WREG0H, _WREG0+1
         .equiv WREG1L, _WREG1
         .equiv WREG1H, _WREG1+1
         .equiv WREG2L, _WREG2
         .equiv WREG2H, _WREG2+1
         .equiv WREG3L, _WREG3
         .equiv WREG3H, _WREG3+1
         .equiv WREG4L, _WREG4
         .equiv WREG4H, _WREG4+1
         .equiv WREG5L, _WREG5
         .equiv WREG5H, _WREG5+1
         .equiv WREG6L, _WREG6
         .equiv WREG6H, _WREG6+1
         .equiv WREG7L, _WREG7
         .equiv WREG7H, _WREG7+1
         .equiv WREG8L, _WREG8
         .equiv WREG8H, _WREG8+1
         .equiv WREG9L, _WREG9
         .equiv WREG9H, _WREG9+1
         .equiv WREG10L, _WREG10
         .equiv WREG10H, _WREG10+1
         .equiv WREG11L, _WREG11
         .equiv WREG11H, _WREG11+1
         .equiv WREG12L, _WREG12
         .equiv WREG12H, _WREG12+1
         .equiv WREG13L, _WREG13
         .equiv WREG13H, _WREG13+1
         .equiv WREG14L, _WREG14
         .equiv WREG14H, _WREG14+1
         .equiv WREG15L, _WREG15
         .equiv WREG15H, _WREG15+1
         .equiv SPLIML, _SPLIM
         .equiv SPLIMH, _SPLIM+1
         .equiv ACCALL, _ACCAL
         .equiv ACCALH, _ACCAL+1
         .equiv ACCAHL, _ACCAH
         .equiv ACCAHH, _ACCAH+1
         .equiv ACCAUL, _ACCAU
         .equiv ACCBLL, _ACCBL
         .equiv ACCBLH, _ACCBL+1
         .equiv ACCBHL, _ACCBH
         .equiv ACCBHH, _ACCBH+1
         .equiv ACCBUL, _ACCBU
         .equiv PCLL, _PCL
         .equiv PCLH, _PCL+1
         .equiv PCHL, _PCH
         .equiv PCHH, _PCH+1
         .equiv TBLPAGL, _TBLPAG
         .equiv TBLPAGH, _TBLPAG+1
         .equiv PSVPAGL, _PSVPAG
         .equiv PSVPAGH, _PSVPAG+1
         .equiv RCOUNTL, _RCOUNT
         .equiv RCOUNTH, _RCOUNT+1
         .equiv DCOUNTL, _DCOUNT
         .equiv DCOUNTH, _DCOUNT+1
         .equiv DOSTARTLL, _DOSTARTL
         .equiv DOSTARTLH, _DOSTARTL+1
         .equiv DOSTARTHL, _DOSTARTH
         .equiv DOSTARTHH, _DOSTARTH+1
         .equiv DOENDLL, _DOENDL
         .equiv DOENDLH, _DOENDL+1
         .equiv DOENDHL, _DOENDH
         .equiv DOENDHH, _DOENDH+1
         .equiv SRL, _SR                        ; See Description in section 1b
         .equiv SRH, _SR+1                      ; See Description in section 1b
         .equiv CORCONL, _CORCON                ; See Description in section 1b
         .equiv MODCONL, _MODCON                ; See Description in section 1b
         .equiv MODCONH, _MODCON+1              ; See Description in section 1b
         .equiv XMODSRTL, _XMODSRT
         .equiv XMODSRTH, _XMODSRT+1
         .equiv XMODENDL, _XMODEND
         .equiv XMODENDH, _XMODEND+1
         .equiv YMODSRTL, _YMODSRT
         .equiv YMODSRTH, _YMODSRT+1
         .equiv YMODENDL, _YMODEND
         .equiv YMODENDH, _YMODEND+1
         .equiv XBREVL, _XBREV                  ; See Description in section 1b
         .equiv XBREVH, _XBREV+1
         .equiv DISICNTL, _DISICNT
         .equiv DISICNTH, _DISICNT+1

;------------------------------------------------------------------------------
; 1b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     SR - Status Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv OA, 0x000F
         .equiv OB, 0x000E
         .equiv SA, 0x000D
         .equiv SB, 0x000C
         .equiv OAB, 0x000B
         .equiv SAB, 0x000A
         .equiv DA, 0x0009
         .equiv DC, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv IPL2, 0x0007
         .equiv IPL1, 0x0006
         .equiv IPL0, 0x0005
         .equiv RA, 0x0004
         .equiv N, 0x0003
         .equiv OV, 0x0002
         .equiv Z, 0x0001
         .equiv C, 0x0000

;------------------------------------------------------------------------------
;     CORCON - Core Configuration Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv US, 0x000C
         .equiv EDT, 0x000B
         .equiv DL2, 0x000A
         .equiv DL1, 0x0009
         .equiv DL0, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv SATA, 0x0007
         .equiv SATB, 0x0006
         .equiv SATDW, 0x0005
         .equiv ACCSAT, 0x0004
         .equiv IPL3, 0x0003
         .equiv PSV, 0x0002
         .equiv RND, 0x0001
         .equiv IF, 0x0000

;------------------------------------------------------------------------------
;     MODCON - Modulo Addressing Mode Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv XMODEN, 0x000F
         .equiv YMODEN, 0x000E

;------------------------------------------------------------------------------
;     XBREV - Bit Reversed Addressing Mode Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv BREN, 0x000F

;==============================================================================
;
; 2.  Interrupt Controller Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 2a. SFR Definitions
;------------------------------------------------------------------------------
         .equiv INTCON1H, _INTCON1+1           ; See description for all
         .equiv INTCON1L, _INTCON1       ;  registers in sub-section below
         .equiv INTCON2H, _INTCON2+1
         .equiv INTCON2L, _INTCON2
         .equiv IFS0H, _IFS0+1
         .equiv IFS0L, _IFS0
         .equiv IFS1H, _IFS1+1
         .equiv IFS1L, _IFS1
         .equiv IFS2H, _IFS2+1
         .equiv IFS2L, _IFS2
         .equiv IEC0H, _IEC0+1
         .equiv IEC0L, _IEC0
         .equiv IEC1H, _IEC1+1
         .equiv IEC1L, _IEC1
         .equiv IEC2H, _IEC2+1
         .equiv IEC2L, _IEC2
         .equiv IPC0H, _IPC0+1
         .equiv IPC0L, _IPC0
         .equiv IPC1H, _IPC1+1
         .equiv IPC1L, _IPC1
         .equiv IPC2H, _IPC2+1
         .equiv IPC2L, _IPC2
         .equiv IPC3H, _IPC3+1
         .equiv IPC3L, _IPC3
         .equiv IPC4H, _IPC4+1
         .equiv IPC4L, _IPC4
         .equiv IPC5H, _IPC5+1
         .equiv IPC5L, _IPC5
         .equiv IPC6H, _IPC6+1
         .equiv IPC6L, _IPC6
         .equiv IPC9H, _IPC9+1
         .equiv IPC10H, _IPC10+1
         .equiv IPC10L, _IPC10

;------------------------------------------------------------------------------
; 2b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     INTCON1 : Interrupt Control Register 1
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv NSTDIS, 0x000F
         .equiv OVATE, 0x000A
         .equiv OVBTE, 0x0009
         .equiv COVTE, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below: