//==========================================================================////      io/serial/sh/scif/sh_scif_serial.c////      SH Serial IRDA/SCIF I/O Interface Module (interrupt driven)////==========================================================================//####ECOSGPLCOPYRIGHTBEGIN####// -------------------------------------------// This file is part of eCos, the Embedded Configurable Operating System.// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.//// eCos is free software; you can redistribute it and/or modify it under// the terms of the GNU General Public License as published by the Free// Software Foundation; either version 2 or (at your option) any later version.//// eCos is distributed in the hope that it will be useful, but WITHOUT ANY// WARRANTY; without even the implied warranty of MERCHANTABILITY or// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License// for more details.//// You should have received a copy of the GNU General Public License along// with eCos; if not, write to the Free Software Foundation, Inc.,// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.//// As a special exception, if other files instantiate templates or use macros// or inline functions from this file, or you compile this file and link it// with other works to produce a work based on this file, this file does not// by itself cause the resulting work to be covered by the GNU General Public// License. However the source code for this file must still be made available// in accordance with section (3) of the GNU General Public License.//// This exception does not invalidate any other reasons why a work based on// this file might be covered by the GNU General Public License.//// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.// at http://sources.redhat.com/ecos/ecos-license/// -------------------------------------------//####ECOSGPLCOPYRIGHTEND####//==========================================================================//#####DESCRIPTIONBEGIN####//// Author(s):   jskov// Contributors:gthomas, jskov// Date:        2000-04-04// Purpose:     SH Serial IRDA/SCIF I/O module (interrupt driven version)// Description: ////####DESCRIPTIONEND####//==========================================================================#include <pkgconf/io_serial.h>#include <pkgconf/io.h>// FIXME: This is necessary since the SCI driver may be overriding// CYGDAT_IO_SERIAL_DEVICE_HEADER. Need a better way to include two// different drivers.#include <pkgconf/io_serial_sh_scif.h>#include <cyg/io/io.h>#include <cyg/hal/hal_intr.h>#include <cyg/io/devtab.h>#include <cyg/infra/diag.h>#include <cyg/infra/cyg_ass.h>#include <cyg/io/serial.h>#include <cyg/hal/sh_regs.h>#include <cyg/hal/hal_cache.h>// Only compile driver if an inline file with driver details was selected.#ifdef CYGDAT_IO_SERIAL_SH_SCIF_INL#if defined(CYGPKG_HAL_SH_SH2)// The SCIF controller register layout on the SH2// The controller base is defined in the board specification file.# define SCIF_SCSMR      0x00      // serial mode register# define SCIF_SCBRR      0x02      // bit rate register     # define SCIF_SCSCR      0x04      // serial control register# define SCIF_SCFTDR     0x06      // transmit data register# define SCIF_SC1SSR     0x08      // serial status register 1# define SCIF_SCSSR      SCIF_SC1SSR# define SCIF_SC2SSR     0x0a      // serial status register 2# define SCIF_SCFRDR     0x0c      // receive data register   # define SCIF_SCFCR      0x0e      // FIFO control            # define SCIF_SCFDR      0x10      // FIFO data count register# define SCIF_SCFER      0x12      // FIFO error register# define SCIF_SCIMR      0x14      // IrDA mode register#elif defined(CYGPKG_HAL_SH_SH3)// The SCIF controller register layout on the SH3// The controller base is defined in the board specification file.# define SCIF_SCSMR      0x00      // serial mode register# define SCIF_SCBRR      0x02      // bit rate register# define SCIF_SCSCR      0x04      // serial control register# define SCIF_SCFTDR     0x06      // transmit data register# define SCIF_SCSSR      0x08      // serial status register# define SCIF_SCFRDR     0x0a      // receive data register# define SCIF_SCFCR      0x0c      // FIFO control# define SCIF_SCFDR      0x0e      // FIFO data count register#else# error "Unsupported variant"#endifstatic short select_word_length[] = {    -1,    -1,    CYGARC_REG_SCIF_SCSMR_CHR,               // 7 bits    0                                   // 8 bits};static short select_stop_bits[] = {    -1,    0,                                  // 1 stop bit    -1,    CYGARC_REG_SCIF_SCSMR_STOP               // 2 stop bits};static short select_parity[] = {    0,                                  // No parity    CYGARC_REG_SCIF_SCSMR_PE,                // Even parity    CYGARC_REG_SCIF_SCSMR_PE|CYGARC_REG_SCIF_SCSMR_OE, // Odd parity    -1,    -1};static unsigned short select_baud[] = {    0,    // Unused    CYGARC_SCBRR_CKSx(50)<<8 | CYGARC_SCBRR_N(50),    CYGARC_SCBRR_CKSx(75)<<8 | CYGARC_SCBRR_N(75),    CYGARC_SCBRR_CKSx(110)<<8 | CYGARC_SCBRR_N(110),    CYGARC_SCBRR_CKSx(134)<<8 | CYGARC_SCBRR_N(134),    CYGARC_SCBRR_CKSx(150)<<8 | CYGARC_SCBRR_N(150),    CYGARC_SCBRR_CKSx(200)<<8 | CYGARC_SCBRR_N(200),    CYGARC_SCBRR_CKSx(300)<<8 | CYGARC_SCBRR_N(300),    CYGARC_SCBRR_CKSx(600)<<8 | CYGARC_SCBRR_N(600),    CYGARC_SCBRR_CKSx(1200)<<8 | CYGARC_SCBRR_N(1200),    CYGARC_SCBRR_CKSx(1800)<<8 | CYGARC_SCBRR_N(1800),    CYGARC_SCBRR_CKSx(2400)<<8 | CYGARC_SCBRR_N(2400),    CYGARC_SCBRR_CKSx(3600)<<8 | CYGARC_SCBRR_N(3600),    CYGARC_SCBRR_CKSx(4800)<<8 | CYGARC_SCBRR_N(4800),    CYGARC_SCBRR_CKSx(7200)<<8 | CYGARC_SCBRR_N(7200),    CYGARC_SCBRR_CKSx(9600)<<8 | CYGARC_SCBRR_N(9600),    CYGARC_SCBRR_CKSx(14400)<<8 | CYGARC_SCBRR_N(14400),    CYGARC_SCBRR_CKSx(19200)<<8 | CYGARC_SCBRR_N(19200),    CYGARC_SCBRR_CKSx(38400)<<8 | CYGARC_SCBRR_N(38400),    CYGARC_SCBRR_CKSx(57600)<<8 | CYGARC_SCBRR_N(57600),    CYGARC_SCBRR_CKSx(115200)<<8 | CYGARC_SCBRR_N(115200),    CYGARC_SCBRR_CKSx(230400)<<8 | CYGARC_SCBRR_N(230400)};typedef struct sh_scif_info {    CYG_WORD          er_int_num,       // Error interrupt number#ifdef CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT                      br_int_num,       // Break interrupt number#endif                      rx_int_num,       // Receive interrupt number                      tx_int_num;       // Transmit interrupt number    CYG_ADDRWORD      ctrl_base;        // Base address of SCI controller    cyg_interrupt     serial_er_interrupt,#ifdef CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT                      serial_br_interrupt,#endif                      serial_rx_interrupt,                      serial_tx_interrupt;    cyg_handle_t      serial_er_interrupt_handle, #ifdef CYGINT_IO_SERIAL_SH_SCIF_BR_INTERRUPT                      serial_br_interrupt_handle, #endif                      serial_rx_interrupt_handle,                       serial_tx_interrupt_handle;    volatile bool     tx_enabled;       // expect tx _serial_ interrupts#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA    bool              irda_mode;#endif#ifdef CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX    bool              async_rxtx_mode;#endif#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMA    cyg_bool          dma_enable;       // Set if DMA mode    cyg_uint32        dma_xmt_cr_flags; // CR flags for DMA mode    CYG_WORD          dma_xmt_int_num;  // DMA xmt completion interrupt    CYG_ADDRWORD      dma_xmt_base;     // Base address of DMA channel    int               dma_xmt_len;      // length transferred by DMA    cyg_interrupt     dma_xmt_interrupt;    cyg_handle_t      dma_xmt_interrupt_handle;    volatile cyg_bool dma_xmt_running;  // expect tx _dma_ interrupts#endif} sh_scif_info;static bool sh_scif_init(struct cyg_devtab_entry *tab);static bool sh_scif_putc(serial_channel *chan, unsigned char c);static Cyg_ErrNo sh_scif_lookup(struct cyg_devtab_entry **tab,                                    struct cyg_devtab_entry *sub_tab,                                   const char *name);static unsigned char sh_scif_getc(serial_channel *chan);static Cyg_ErrNo sh_scif_set_config(serial_channel *chan, cyg_uint32 key,                                     const void *xbuf, cyg_uint32 *len);static void sh_scif_start_xmit(serial_channel *chan);static void sh_scif_stop_xmit(serial_channel *chan);static cyg_uint32 sh_scif_tx_ISR(cyg_vector_t vector, cyg_addrword_t data);static void       sh_scif_tx_DSR(cyg_vector_t vector, cyg_ucount32 count,                                    cyg_addrword_t data);static cyg_uint32 sh_scif_rx_ISR(cyg_vector_t vector, cyg_addrword_t data);static void       sh_scif_rx_DSR(cyg_vector_t vector, cyg_ucount32 count,                                    cyg_addrword_t data);static cyg_uint32 sh_scif_er_ISR(cyg_vector_t vector, cyg_addrword_t data);static void       sh_scif_er_DSR(cyg_vector_t vector, cyg_ucount32 count,                                    cyg_addrword_t data);#ifdef CYGINT_IO_SERIAL_SH_SCIF_DMAstatic cyg_uint32 sh_dma_xmt_ISR(cyg_vector_t vector, cyg_addrword_t data);static void       sh_dma_xmt_DSR(cyg_vector_t vector, cyg_ucount32 count,                                  cyg_addrword_t data);#endifstatic SERIAL_FUNS(sh_scif_funs,                    sh_scif_putc,                    sh_scif_getc,                   sh_scif_set_config,                   sh_scif_start_xmit,                   sh_scif_stop_xmit    );// Get the board specification#include CYGDAT_IO_SERIAL_SH_SCIF_INL// Allow platform to define handling of additional config keys#ifndef CYGPRI_DEVS_SH_SCIF_SET_CONFIG_PLF# define CYGPRI_DEVS_SH_SCIF_SET_CONFIG_PLF#endif// Internal function to actually configure the hardware to desired baud rate,// etc.static boolsh_scif_config_port(serial_channel *chan, cyg_serial_info_t *new_config,                      bool init){    cyg_uint16 baud_divisor = select_baud[new_config->baud];    sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv;    cyg_uint8 _scr, _smr;    cyg_uint16 _sr;    CYG_ADDRWORD base = sh_chan->ctrl_base;    // Check configuration request    if ((-1 == select_word_length[(new_config->word_length -                                  CYGNUM_SERIAL_WORD_LENGTH_5)])        || -1 == select_stop_bits[new_config->stop]        || -1 == select_parity[new_config->parity]        || baud_divisor == 0)        return false;    // Disable SCI interrupts while changing hardware    HAL_READ_UINT8(base+SCIF_SCSCR, _scr);    HAL_WRITE_UINT8(base+SCIF_SCSCR, 0);    // Reset FIFO.    HAL_WRITE_UINT8(base+SCIF_SCFCR,                     CYGARC_REG_SCIF_SCFCR_TFRST|CYGARC_REG_SCIF_SCFCR_RFRST);#ifdef CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX    sh_chan->async_rxtx_mode = false;#endif#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA    if (sh_chan->irda_mode) {        // In IrDA mode, the configuration is hardwired and the mode        // bits should not be set#ifdef CYGARC_REG_SCIF_SCSMR_IRMOD        _smr = CYGARC_REG_SCIF_SCSMR_IRMOD;#elif defined(SCIF_SCIMR)        _smr = 0;        HAL_WRITE_UINT8(base+SCIF_SCIMR, CYGARC_REG_SCIF_SCIMR_IRMOD);#endif    } else#endif    {        // Set databits, stopbits and parity.        _smr = select_word_length[(new_config->word_length -                                   CYGNUM_SERIAL_WORD_LENGTH_5)] |             select_stop_bits[new_config->stop] |            select_parity[new_config->parity];#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA#ifdef SCIF_SCIMR        // Disable IrDA mode        HAL_WRITE_UINT8(base+SCIF_SCIMR, 0);#endif#endif    }    HAL_WRITE_UINT8(base+SCIF_SCSMR, _smr);    // Set baud rate.    _smr &= ~CYGARC_REG_SCIF_SCSMR_CKSx_MASK;    _smr |= baud_divisor >> 8;    HAL_WRITE_UINT8(base+SCIF_SCSMR, _smr);    HAL_WRITE_UINT8(base+SCIF_SCBRR, baud_divisor & 0xff);    // FIXME: Should delay 1/<baud> second here.    // Clear the status register (read first).    HAL_READ_UINT16(base+SCIF_SCSSR, _sr);    HAL_WRITE_UINT16(base+SCIF_SCSSR, 0);    // Bring FIFO out of reset and set FIFO trigger marks    //    // Note that the RX FIFO size must be smaller when flow control is    // enabled. This due to observations made by running the flow2    // serial test. The automatic RTS de-assertion happens    // (apparently) when the FIFO fills past the trigger count -    // causing the sender to stop transmission. But there's a lag    // before transmission is stopped, and if the FIFO fills in that    // time, data will be lost. Thus, seeing as HW flow control is    // presumed used for prevention of data loss, set the trigger    // level so the sender has time to stop transmission before the    // FIFO fills up.    //    // The trigger setting of 8 allows test flow2 to complete without    // problems. It tests duplex data transmission at 115200    // baud. Depending on the lag time between the de-assertion of RTS    // and actual transmission stop, it may be necessary to reduce the    // trigger level further.#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW    HAL_WRITE_UINT8(base+SCIF_SCFCR,                     CYGARC_REG_SCIF_SCFCR_RTRG_8|CYGARC_REG_SCIF_SCFCR_TTRG_8);#else    HAL_WRITE_UINT8(base+SCIF_SCFCR,                     CYGARC_REG_SCIF_SCFCR_RTRG_14|CYGARC_REG_SCIF_SCFCR_TTRG_8);#endif    if (init) {        // Always enable received and (for normal mode) transmitter        _scr = CYGARC_REG_SCIF_SCSCR_TE | CYGARC_REG_SCIF_SCSCR_RE;#ifdef CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX        if (sh_chan->async_rxtx_mode)            _scr = CYGARC_REG_SCIF_SCSCR_RE;#endif#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA        if (sh_chan->irda_mode)            _scr = CYGARC_REG_SCIF_SCSCR_RE;#endif        if (chan->in_cbuf.len != 0)            _scr |= CYGARC_REG_SCIF_SCSCR_RIE; // enable rx interrupts    }         HAL_WRITE_UINT8(base+SCIF_SCSCR, _scr);    if (new_config != &chan->config) {        chan->config = *new_config;    }    return true;}// Function to initialize the device.  Called at bootstrap time.static bool sh_scif_init(struct cyg_devtab_entry *tab){    serial_channel *chan = (serial_channel *)tab->priv;