//==========================================================================////      spr_defs.h////      Defines OR1K architecture specific special-purpose registers (SPRs)////==========================================================================//####ECOSGPLCOPYRIGHTBEGIN####// -------------------------------------------// This file is part of eCos, the Embedded Configurable Operating System.// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.//// eCos is free software; you can redistribute it and/or modify it under// the terms of the GNU General Public License as published by the Free// Software Foundation; either version 2 or (at your option) any later version.//// eCos is distributed in the hope that it will be useful, but WITHOUT ANY// WARRANTY; without even the implied warranty of MERCHANTABILITY or// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License// for more details.//// You should have received a copy of the GNU General Public License along// with eCos; if not, write to the Free Software Foundation, Inc.,// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.//// As a special exception, if other files instantiate templates or use macros// or inline functions from this file, or you compile this file and link it// with other works to produce a work based on this file, this file does not// by itself cause the resulting work to be covered by the GNU General Public// License. However the source code for this file must still be made available// in accordance with section (3) of the GNU General Public License.//// This exception does not invalidate any other reasons why a work based on// this file might be covered by the GNU General Public License.//// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.// at http://sources.redhat.com/ecos/ecos-license/// -------------------------------------------//####ECOSGPLCOPYRIGHTEND####//==========================================================================//#####DESCRIPTIONBEGIN####//// Author(s):    sfurman// Contributors: Damjan Lambert// Date:         2003-01-17// Purpose:      Define OpenRISC architecture special-purpose registers// Usage:        #include <cyg/hal/hal_arch.h>//              //####DESCRIPTIONEND####////==========================================================================/* Definition of special-purpose registers (SPRs) */#ifndef _ASM_SPR_DEFS_H#define _ASM_SPR_DEFS_H#define MAX_GRPS (32)#define MAX_SPRS_PER_GRP_BITS (11)#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)#define MAX_SPRS (0x10000) /* Base addresses for the groups */#define SPRGROUP_SYS    (0<< MAX_SPRS_PER_GRP_BITS)#define SPRGROUP_DMMU   (1<< MAX_SPRS_PER_GRP_BITS)#define SPRGROUP_IMMU   (2<< MAX_SPRS_PER_GRP_BITS)#define SPRGROUP_DC     (3<< MAX_SPRS_PER_GRP_BITS)#define SPRGROUP_IC     (4<< MAX_SPRS_PER_GRP_BITS)#define SPRGROUP_MAC    (5<< MAX_SPRS_PER_GRP_BITS)#define SPRGROUP_D      (6<< MAX_SPRS_PER_GRP_BITS)#define SPRGROUP_PC     (7<< MAX_SPRS_PER_GRP_BITS)#define SPRGROUP_PM     (8<< MAX_SPRS_PER_GRP_BITS)#define SPRGROUP_PIC    (9<< MAX_SPRS_PER_GRP_BITS)#define SPRGROUP_TT     (10<< MAX_SPRS_PER_GRP_BITS)/* System control and status group */#define SPR_VR          (SPRGROUP_SYS + 0)#define SPR_UPR         (SPRGROUP_SYS + 1)#define SPR_PC          (SPRGROUP_SYS + 16)  /* CZ 21/06/01 */#define SPR_SR          (SPRGROUP_SYS + 17)  /* CZ 21/06/01 */#define SPR_EPCR_BASE   (SPRGROUP_SYS + 32)  /* CZ 21/06/01 */#define SPR_EPCR_LAST   (SPRGROUP_SYS + 47)  /* CZ 21/06/01 */#define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)#define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)#define SPR_ESR_BASE    (SPRGROUP_SYS + 64)#define SPR_ESR_LAST    (SPRGROUP_SYS + 79)#if 0/* Data MMU group */#define SPR_DMMUCR      (SPRGROUP_DMMU + 0)#define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200)#define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200)#define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200)#define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200)/* Instruction MMU group */#define SPR_IMMUCR      (SPRGROUP_IMMU + 0)#define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200)#define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200)#define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200)#define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200)#else/* Data MMU group */#define SPR_DMMUCR      (SPRGROUP_DMMU + 0)#define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)#define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)#define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)#define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)/* Instruction MMU group */#define SPR_IMMUCR      (SPRGROUP_IMMU + 0)#define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)#define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)#define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)#define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)#endif/* Data cache group */#define SPR_DCCR        (SPRGROUP_DC + 0)#define SPR_DCBPR       (SPRGROUP_DC + 1)#define SPR_DCBFR       (SPRGROUP_DC + 2)#define SPR_DCBIR       (SPRGROUP_DC + 3)#define SPR_DCBWR       (SPRGROUP_DC + 4)#define SPR_DCBLR       (SPRGROUP_DC + 5)#define SPR_DCR_BASE(WAY)       (SPRGROUP_DC + 0x200 + (WAY) * 0x200)#define SPR_DCR_LAST(WAY)       (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)/* Instruction cache group */#define SPR_ICCR        (SPRGROUP_IC + 0)#define SPR_ICBPR       (SPRGROUP_IC + 1)#define SPR_ICBIR       (SPRGROUP_IC + 2)#define SPR_ICBLR       (SPRGROUP_IC + 3)#define SPR_ICR_BASE(WAY)       (SPRGROUP_IC + 0x200 + (WAY) * 0x200)#define SPR_ICR_LAST(WAY)       (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)/* MAC group */#define SPR_MACLO       (SPRGROUP_MAC + 1)#define SPR_MACHI       (SPRGROUP_MAC + 2)/* Debug group */#define SPR_DVR(N)      (SPRGROUP_D + (N))#define SPR_DCR(N)      (SPRGROUP_D + 8 + (N))#define SPR_DMR1        (SPRGROUP_D + 16)#define SPR_DMR2        (SPRGROUP_D + 17)#define SPR_DWCR0       (SPRGROUP_D + 18)#define SPR_DWCR1       (SPRGROUP_D + 19)#define SPR_DSR         (SPRGROUP_D + 20)#define SPR_DRR         (SPRGROUP_D + 21)#define SPR_DIR         (SPRGROUP_D + 22)/* Performance counters group */#define SPR_PCCR(N)     (SPRGROUP_PC + (N))#define SPR_PCMR(N)     (SPRGROUP_PC + 8 + (N))/* Power management group */#define SPR_PMR (SPRGROUP_PM + 0)/* PIC group */#define SPR_PICMR (SPRGROUP_PIC + 0)#define SPR_PICPR (SPRGROUP_PIC + 1)#define SPR_PICSR (SPRGROUP_PIC + 2)/* Tick Timer group */#define SPR_TTMR (SPRGROUP_TT + 0)#define SPR_TTCR (SPRGROUP_TT + 1)/* * Bit definitions for the Version Register * */#define SPR_VR_VER      0xffff0000  /* Processor version */#define SPR_VR_REV      0x0000003f  /* Processor revision *//* * Bit definitions for the Unit Present Register * */#define SPR_UPR_UP      0x00000001  /* UPR present */#define SPR_UPR_DCP     0x00000002  /* Data cache present */#define SPR_UPR_ICP     0x00000004  /* Instruction cache present */#define SPR_UPR_DMP     0x00000008  /* Data MMU present */#define SPR_UPR_IMP     0x00000010  /* Instruction MMU present */#define SPR_UPR_OB32P   0x00000020  /* ORBIS32 present */#define SPR_UPR_OB64P   0x00000040  /* ORBIS64 present */#define SPR_UPR_OF32P   0x00000080  /* ORFPX32 present */#define SPR_UPR_OF64P   0x00000100  /* ORFPX64 present */#define SPR_UPR_OV32P   0x00000200  /* ORVDX32 present */#define SPR_UPR_OV64P   0x00000400  /* ORVDX64 present */#define SPR_UPR_DUP     0x00000800  /* Debug unit present */#define SPR_UPR_PCUP    0x00001000  /* Performance counters unit present */#define SPR_UPR_PMP     0x00002000  /* Power management present */#define SPR_UPR_PICP    0x00004000  /* PIC present */#define SPR_UPR_TTP     0x00008000  /* Tick timer present */#define SPR_UPR_SRP     0x00010000  /* Shadow registers present */#define SPR_UPR_RES     0x00fe0000  /* ORVDX32 present */#define SPR_UPR_CUST    0xff000000  /* Custom units *//* * Bit definitions for the Supervision Register * */#define SPR_SR_CID      0xf0000000  /* Context ID */#define SPR_SR_FO       0x00008000  /* Fixed one */#define SPR_SR_EPH      0x00004000  /* Exception Prefixi High */#define SPR_SR_DSX      0x00002000  /* Delay Slot Exception */#define SPR_SR_OVE      0x00001000  /* Overflow flag Exception */#define SPR_SR_OV       0x00000800  /* Overflow flag */#define SPR_SR_CY       0x00000400  /* Carry flag */#define SPR_SR_F        0x00000200  /* Condition Flag */#define SPR_SR_CE       0x00000100  /* CID Enable */#define SPR_SR_LEE      0x00000080  /* Little Endian Enable */#define SPR_SR_IME      0x00000040  /* Instruction MMU Enable */#define SPR_SR_DME      0x00000020  /* Data MMU Enable */#define SPR_SR_ICE      0x00000010  /* Instruction Cache Enable */#define SPR_SR_DCE      0x00000008  /* Data Cache Enable */#define SPR_SR_IEE      0x00000004  /* Interrupt Exception Enable */#define SPR_SR_TEE      0x00000002  /* Tick timer Exception Enable */#define SPR_SR_SM       0x00000001  /* Supervisor Mode */#define SPR_SR_FO_BIT    15#define SPR_SR_EPH_BIT   14#define SPR_SR_DSX_BIT   13#define SPR_SR_OVE_BIT   12#define SPR_SR_OV_BIT    11#define SPR_SR_CY_BIT    10#define SPR_SR_F_BIT     9#define SPR_SR_CE_BIT    8#define SPR_SR_LEE_BIT   7#define SPR_SR_IME_BIT   6#define SPR_SR_DME_BIT   5#define SPR_SR_ICE_BIT   4#define SPR_SR_DCE_BIT   3#define SPR_SR_IEE_BIT   2#define SPR_SR_TEE_BIT   1#define SPR_SR_SM_BIT    0