/* * Bit definitions for the Data MMU Control Register * */#define SPR_DMMUCR_P2S  0x0000003e  /* Level 2 Page Size */#define SPR_DMMUCR_P1S  0x000007c0  /* Level 1 Page Size */#define SPR_DMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */#define SPR_DMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width *//* * Bit definitions for the Instruction MMU Control Register * */#define SPR_IMMUCR_P2S  0x0000003e  /* Level 2 Page Size */#define SPR_IMMUCR_P1S  0x000007c0  /* Level 1 Page Size */#define SPR_IMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */#define SPR_IMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width *//* * Bit definitions for the Data TLB Match Register * */#define SPR_DTLBMR_V    0x00000001  /* Valid */#define SPR_DTLBMR_PL1  0x00000002  /* Page Level 1 (if 0 then PL2) */#define SPR_DTLBMR_CID  0x0000003c  /* Context ID */#define SPR_DTLBMR_LRU  0x000000c0  /* Least Recently Used */#define SPR_DTLBMR_VPN  0xfffff000  /* Virtual Page Number *//* * Bit definitions for the Data TLB Translate Register * */#define SPR_DTLBTR_CC   0x00000001  /* Cache Coherency */#define SPR_DTLBTR_CI   0x00000002  /* Cache Inhibit */#define SPR_DTLBTR_WBC  0x00000004  /* Write-Back Cache */#define SPR_DTLBTR_WOM  0x00000008  /* Weakly-Ordered Memory */#define SPR_DTLBTR_A    0x00000010  /* Accessed */#define SPR_DTLBTR_D    0x00000020  /* Dirty */#define SPR_DTLBTR_URE  0x00000040  /* User Read Enable */#define SPR_DTLBTR_UWE  0x00000080  /* User Write Enable */#define SPR_DTLBTR_SRE  0x00000100  /* Supervisor Read Enable */#define SPR_DTLBTR_SWE  0x00000200  /* Supervisor Write Enable */#define SPR_DTLBTR_PPN  0xfffff000  /* Physical Page Number */#define DTLBTR_NO_LIMIT ( SPR_DTLBTR_URE |  \                          SPR_DTLBTR_UWE |  \                          SPR_DTLBTR_SRE |  \                          SPR_DTLBTR_SWE )/* * Bit definitions for the Instruction TLB Match Register * */#define SPR_ITLBMR_V    0x00000001  /* Valid */#define SPR_ITLBMR_PL1  0x00000002  /* Page Level 1 (if 0 then PL2) */#define SPR_ITLBMR_CID  0x0000003c  /* Context ID */#define SPR_ITLBMR_LRU  0x000000c0  /* Least Recently Used */#define SPR_ITLBMR_VPN  0xfffff000  /* Virtual Page Number *//* * Bit definitions for the Instruction TLB Translate Register * */#define SPR_ITLBTR_CC   0x00000001  /* Cache Coherency */#define SPR_ITLBTR_CI   0x00000002  /* Cache Inhibit */#define SPR_ITLBTR_WBC  0x00000004  /* Write-Back Cache */#define SPR_ITLBTR_WOM  0x00000008  /* Weakly-Ordered Memory */#define SPR_ITLBTR_A    0x00000010  /* Accessed */#define SPR_ITLBTR_D    0x00000020  /* Dirty */#define SPR_ITLBTR_SXE  0x00000040  /* User Read Enable */#define SPR_ITLBTR_UXE  0x00000080  /* User Write Enable */#define SPR_ITLBTR_PPN  0xfffff000  /* Physical Page Number */#define ITLBTR_NO_LIMIT (SPR_ITLBTR_SXE | SPR_ITLBTR_UXE)/* * Bit definitions for Data Cache Control register * */#define SPR_DCCR_EW     0x000000ff  /* Enable ways *//* * Bit definitions for Insn Cache Control register * */#define SPR_ICCR_EW     0x000000ff  /* Enable ways *//* * Bit definitions for Debug Control registers * */#define SPR_DCR_DP      0x00000001  /* DVR/DCR present */#define SPR_DCR_CC      0x0000000e  /* Compare condition */#define SPR_DCR_SC      0x00000010  /* Signed compare */#define SPR_DCR_CT      0x000000e0  /* Compare to *//* * Bit definitions for Debug Mode 1 register * */#define SPR_DMR1_CW0    0x00000003  /* Chain watchpoint 0 */#define SPR_DMR1_CW1    0x0000000c  /* Chain watchpoint 1 */#define SPR_DMR1_CW2    0x00000030  /* Chain watchpoint 2 */#define SPR_DMR1_CW3    0x000000c0  /* Chain watchpoint 3 */#define SPR_DMR1_CW4    0x00000300  /* Chain watchpoint 4 */#define SPR_DMR1_CW5    0x00000c00  /* Chain watchpoint 5 */#define SPR_DMR1_CW6    0x00003000  /* Chain watchpoint 6 */#define SPR_DMR1_CW7    0x0000c000  /* Chain watchpoint 7 */#define SPR_DMR1_CW8    0x00030000  /* Chain watchpoint 8 */#define SPR_DMR1_CW9    0x000c0000  /* Chain watchpoint 9 */#define SPR_DMR1_CW10   0x00300000  /* Chain watchpoint 10 */#define SPR_DMR1_ST     0x00400000  /* Single-step trace*/#define SPR_DMR1_BT     0x00800000  /* Branch trace */#define SPR_DMR1_DXFW   0x01000000  /* Disable external force watchpoint *//* * Bit definitions for Debug Mode 2 register * */#define SPR_DMR2_WCE0   0x00000001  /* Watchpoint counter 0 enable */#define SPR_DMR2_WCE1   0x00000002  /* Watchpoint counter 0 enable */#define SPR_DMR2_AWTC   0x00001ffc  /* Assign watchpoints to counters */#define SPR_DMR2_WGB    0x00ffe000  /* Watchpoints generating breakpoint *//* * Bit definitions for Debug watchpoint counter registers * */#define SPR_DWCR_COUNT  0x0000ffff  /* Count */#define SPR_DWCR_MATCH  0xffff0000  /* Match *//* * Bit definitions for Debug stop register * */#define SPR_DSR_RSTE    0x00000001  /* Reset exception */#define SPR_DSR_BUSEE   0x00000002  /* Bus error exception */#define SPR_DSR_DPFE    0x00000004  /* Data Page Fault exception */#define SPR_DSR_IPFE    0x00000008  /* Insn Page Fault exception */#define SPR_DSR_LPINTE  0x00000010  /* Low priority interrupt exception */#define SPR_DSR_AE      0x00000020  /* Alignment exception */#define SPR_DSR_IIE     0x00000040  /* Illegal Instruction exception */#define SPR_DSR_HPINTE  0x00000080  /* High priority interrupt exception */#define SPR_DSR_DME     0x00000100  /* DTLB miss exception */#define SPR_DSR_IME     0x00000200  /* ITLB miss exception */#define SPR_DSR_RE      0x00000400  /* Range exception */#define SPR_DSR_SCE     0x00000800  /* System call exception */#define SPR_DSR_BE      0x00001000  /* Breakpoint exception *//* * Bit definitions for Debug reason register * */#define SPR_DRR_RSTE    0x00000001  /* Reset exception */#define SPR_DRR_BUSEE   0x00000002  /* Bus error exception */#define SPR_DRR_DPFE    0x00000004  /* Data Page Fault exception */#define SPR_DRR_IPFE    0x00000008  /* Insn Page Fault exception */#define SPR_DRR_LPINTE  0x00000010  /* Low priority interrupt exception */#define SPR_DRR_AE      0x00000020  /* Alignment exception */#define SPR_DRR_IIE     0x00000040  /* Illegal Instruction exception */#define SPR_DRR_HPINTE  0x00000080  /* High priority interrupt exception */#define SPR_DRR_DME     0x00000100  /* DTLB miss exception */#define SPR_DRR_IME     0x00000200  /* ITLB miss exception */#define SPR_DRR_RE      0x00000400  /* Range exception */#define SPR_DRR_SCE     0x00000800  /* System call exception */#define SPR_DRR_BE      0x00001000  /* Breakpoint exception *//* * Bit definitions for Performance counters mode registers * */#define SPR_PCMR_CP     0x00000001  /* Counter present */#define SPR_PCMR_UMRA   0x00000002  /* User mode read access */#define SPR_PCMR_CISM   0x00000004  /* Count in supervisor mode */#define SPR_PCMR_CIUM   0x00000008  /* Count in user mode */#define SPR_PCMR_LA     0x00000010  /* Load access event */#define SPR_PCMR_SA     0x00000020  /* Store access event */#define SPR_PCMR_IF     0x00000040  /* Instruction fetch event*/#define SPR_PCMR_DCM    0x00000080  /* Data cache miss event */#define SPR_PCMR_ICM    0x00000100  /* Insn cache miss event */#define SPR_PCMR_IFS    0x00000200  /* Insn fetch stall event */#define SPR_PCMR_LSUS   0x00000400  /* LSU stall event */#define SPR_PCMR_BS     0x00000800  /* Branch stall event */#define SPR_PCMR_DTLBM  0x00001000  /* DTLB miss event */#define SPR_PCMR_ITLBM  0x00002000  /* ITLB miss event */#define SPR_PCMR_DDS    0x00004000  /* Data dependency stall event */#define SPR_PCMR_WPE    0x03ff8000  /* Watchpoint events *//*  * Bit definitions for the Power management register * */#define SPR_PMR_SDF     0x00000001  /* Slow down factor */#define SPR_PMR_DME     0x00000002  /* Doze mode enable */#define SPR_PMR_SME     0x00000004  /* Sleep mode enable */#define SPR_PMR_DCGE    0x00000008  /* Dynamic clock gating enable */#define SPR_PMR_SUME    0x00000010  /* Suspend mode enable *//* * Bit definitions for PICMR * */#define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask *//* * Bit definitions for PICPR * */#define SPR_PICPR_IPRIO 0xfffffffc  /* Interrupt priority *//* * Bit definitions for PICSR * */#define SPR_PICSR_IS    0xffffffff  /* Interrupt status *//* * Bit definitions for Tick Timer Control Register * */#define SPR_TTCR_PERIOD 0x0fffffff  /* Time Period */#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD#define SPR_TTMR_IP 0x10000000  /* Interrupt Pending */#define SPR_TTMR_IE 0x20000000  /* Interrupt Enable */#define SPR_TTMR_RT 0x40000000  /* Restart tick */#define SPR_TTMR_SR     0x80000000  /* Single run */#define SPR_TTMR_CR     0xc0000000  /* Continuous run */#define SPR_TTMR_M      0xc0000000  /* Tick mode */#endif// EOF spr_defs.h