{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 20 12:20:30 2012 " "Info: Processing started: Wed Jun 20 12:20:30 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top -c top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "transmiter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file transmiter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 transmiter-behav " "Info: Found design unit 1: transmiter-behav" {  } { { "transmiter.vhd" "" { Text "D:/vhdl/vhdl/uart/top/transmiter.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 transmiter " "Info: Found entity 1: transmiter" {  } { { "transmiter.vhd" "" { Text "D:/vhdl/vhdl/uart/top/transmiter.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fzdiv.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fzdiv.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fzdiv-behav " "Info: Found design unit 1: fzdiv-behav" {  } { { "fzdiv.vhd" "" { Text "D:/vhdl/vhdl/uart/top/fzdiv.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 fzdiv " "Info: Found entity 1: fzdiv" {  } { { "fzdiv.vhd" "" { Text "D:/vhdl/vhdl/uart/top/fzdiv.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "recver.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file recver.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 recver-behav " "Info: Found design unit 1: recver-behav" {  } { { "recver.vhd" "" { Text "D:/vhdl/vhdl/uart/top/recver.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 recver " "Info: Found entity 1: recver" {  } { { "recver.vhd" "" { Text "D:/vhdl/vhdl/uart/top/recver.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 top-sys " "Info: Found design unit 1: top-sys" {  } { { "top.vhd" "" { Text "D:/vhdl/vhdl/uart/top/top.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 top " "Info: Found entity 1: top" {  } { { "top.vhd" "" { Text "D:/vhdl/vhdl/uart/top/top.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Error" "EVRFX_VHDL_BLOCK_PORT_GENERIC_POSITION_ASSIGN_CANNOT_FOLLOW_NAMED" "top.vhd(50) " "Error (10437): VHDL Association List error at top.vhd(50): positional associations must be listed before named associations" {  } { { "top.vhd" "" { Text "D:/vhdl/vhdl/uart/top/top.vhd" 50 0 0 } }  } 0 10437 "VHDL Association List error at %1!s!: positional associations must be listed before named associations" 0 0 "" 0 -1}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "186 " "Error: Peak virtual memory: 186 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Wed Jun 20 12:20:32 2012 " "Error: Processing ended: Wed Jun 20 12:20:32 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}