library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity second is
port(reset,clk,setmin:in std_logic;
	enmin:out std_logic;
	daout:out std_logic_vector(7 downto 0));
end second;
architecture behave of second is
begin
process(reset,clk,setmin)
variable da1:std_logic_vector(3 downto 0);
variable da2:std_Logic_vector(3 downto 0);
begin
if(reset='0')then da1:="0000";da2:="0000";enmin<='0';
else 
	if(clk'event and clk='1') then da1:=da1+1;
		if(da1>"1001") then da2:=da2+1;da1:="0000";
				if(da2>"0101") then enmin<='1';da1:="0000";da2:="0000";
				else enmin<='0';
				end if;
		end if;
		if(setmin='1') then enmin<='1';
		end if;
	end if;
end if;
daout(7 downto 4)<=da2;
daout(3 downto 0)<=da1;
end process;
end behave;