/** * @file IxNpeMhConfig_p.h * * @author Intel Corporation * @date 18 Jan 2002 * * @brief This file contains the private API for the Configuration module. * *  * @par * IXP400 SW Release version 2.0 *  * -- Copyright Notice -- *  * @par * Copyright 2001-2005, Intel Corporation. * All rights reserved. *  * @par * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright *    notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright *    notice, this list of conditions and the following disclaimer in the *    documentation and/or other materials provided with the distribution. * 3. Neither the name of the Intel Corporation nor the names of its contributors *    may be used to endorse or promote products derived from this software *    without specific prior written permission. *  * @par * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. *  * @par * -- End of Copyright Notice --*//** * @defgroup IxNpeMhConfig_p IxNpeMhConfig_p * * @brief The private API for the Configuration module. *  * @{ */#ifndef IXNPEMHCONFIG_P_H#define IXNPEMHCONFIG_P_H#include "IxOsal.h"#include "IxNpeMh.h"#include "IxNpeMhMacros_p.h"/* * inline definition *//* enable function inlining for performances */#ifdef IXNPEMHSOLICITEDCBMGR_C/* Non-inline functions will be defined in this translation unit. 	 Reason is that in GNU Compiler, if the Optimization is turn off, all extern inline	 functions will not be compiled.*/#		ifndef __wince#			ifndef IXNPEMHCONFIG_INLINE#				define IXNPEMHCONFIG_INLINE #			endif#		else#			ifndef IXNPEMHCONFIG_INLINE#				define IXNPEMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN#			endif#		endif /* __wince*/#else#		ifndef IXNPEMHCONFIG_INLINE#			define IXNPEMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN#		endif /* IXNPEMHCONFIG_INLINE */#endif /* IXNPEMHSOLICITEDCBMGR_C *//* * Typedefs and #defines, etc. */ typedef void (*IxNpeMhConfigIsr) (int); /**< ISR function pointer *//** * @struct IxNpeMhConfigNpeInfo * * @brief This structure is used to maintain the configuration information * associated with an NPE. */typedef struct{    IxOsalMutex mutex;          /**< mutex */    UINT32 interruptId;     /**< interrupt ID */    UINT32 virtualRegisterBase; /**< register virtual base address */    UINT32 statusRegister;      /**< status register virtual address */    UINT32 controlRegister;     /**< control register virtual address */    UINT32 inFifoRegister;      /**< inFIFO register virutal address */    UINT32 outFifoRegister;     /**< outFIFO register virtual address */    IxNpeMhConfigIsr isr;   /**< isr routine for handling interrupt */    BOOL oldInterruptState; /**< old interrupt state (TRUE => enabled) */} IxNpeMhConfigNpeInfo;/* * #defines for function return types, etc. *//**< NPE register base address */#define IX_NPEMH_NPE_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE)#define IX_NPEMH_NPEA_OFFSET (0x6000) /**< NPE-A register base offset */#define IX_NPEMH_NPEB_OFFSET (0x7000) /**< NPE-B register base offset */#define IX_NPEMH_NPEC_OFFSET (0x8000) /**< NPE-C register base offset */#define IX_NPEMH_NPESTAT_OFFSET (0x002C) /**< NPE status register offset */#define IX_NPEMH_NPECTL_OFFSET  (0x0030) /**< NPE control register offset */#define IX_NPEMH_NPEFIFO_OFFSET (0x0038) /**< NPE FIFO register offset *//** NPE-A register base address */#define IX_NPEMH_NPEA_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEA_OFFSET)/** NPE-B register base address */#define IX_NPEMH_NPEB_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEB_OFFSET)/** NPE-C register base address */#define IX_NPEMH_NPEC_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEC_OFFSET)/* NPE-A configuration *//** NPE-A interrupt */#define IX_NPEMH_NPEA_INT  (IX_OSAL_IXP400_NPEA_IRQ_LVL)/** NPE-A FIFO register */#define IX_NPEMH_NPEA_FIFO (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPEFIFO_OFFSET)/** NPE-A control register */#define IX_NPEMH_NPEA_CTL  (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPECTL_OFFSET)/** NPE-A status register */#define IX_NPEMH_NPEA_STAT (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPESTAT_OFFSET)/* NPE-B configuration *//** NPE-B interrupt */#define IX_NPEMH_NPEB_INT  (IX_OSAL_IXP400_NPEB_IRQ_LVL)/** NPE-B FIFO register */#define IX_NPEMH_NPEB_FIFO (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPEFIFO_OFFSET)/** NPE-B control register */#define IX_NPEMH_NPEB_CTL  (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPECTL_OFFSET)/** NPE-B status register */#define IX_NPEMH_NPEB_STAT (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPESTAT_OFFSET)/* NPE-C configuration *//** NPE-C interrupt */#define IX_NPEMH_NPEC_INT  (IX_OSAL_IXP400_NPEC_IRQ_LVL)/** NPE-C FIFO register */#define IX_NPEMH_NPEC_FIFO (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPEFIFO_OFFSET)/** NPE-C control register */#define IX_NPEMH_NPEC_CTL  (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPECTL_OFFSET)/** NPE-C status register */#define IX_NPEMH_NPEC_STAT (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPESTAT_OFFSET)/* NPE control register bit definitions */#define IX_NPEMH_NPE_CTL_OFE   (1 << 16) /**< OutFifoEnable */#define IX_NPEMH_NPE_CTL_IFE   (1 << 17) /**< InFifoEnable */#define IX_NPEMH_NPE_CTL_OFEWE (1 << 24) /**< OutFifoEnableWriteEnable */#define IX_NPEMH_NPE_CTL_IFEWE (1 << 25) /**< InFifoEnableWriteEnable *//* NPE status register bit definitions */#define IX_NPEMH_NPE_STAT_OFNE  (1 << 16) /**< OutFifoNotEmpty */#define IX_NPEMH_NPE_STAT_IFNF  (1 << 17) /**< InFifoNotFull */#define IX_NPEMH_NPE_STAT_OFNF  (1 << 18) /**< OutFifoNotFull */#define IX_NPEMH_NPE_STAT_IFNE  (1 << 19) /**< InFifoNotEmpty */#define IX_NPEMH_NPE_STAT_MBINT (1 << 20) /**< Mailbox interrupt */#define IX_NPEMH_NPE_STAT_IFINT (1 << 21) /**< InFifo interrupt */#define IX_NPEMH_NPE_STAT_OFINT (1 << 22) /**< OutFifo interrupt */#define IX_NPEMH_NPE_STAT_WFINT (1 << 23) /**< WatchFifo interrupt *//** * Variable declarations.  Externs are followed by static variables. */extern IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES];/* * Prototypes for interface functions. *//** * @fn void ixNpeMhConfigInitialize (           IxNpeMhNpeInterrupts npeInterrupts) * * @brief This function initialises the Configuration module. * * @param IxNpeMhNpeInterrupts npeInterrupts (in) - whether or not to * service the NPE "outFIFO not empty" interrupts. * * @return No return value. */void ixNpeMhConfigInitialize (    IxNpeMhNpeInterrupts npeInterrupts);/** * @fn void ixNpeMhConfigUninit (void) * * @brief This function uninitialises the Configuration module. * * @return No return value. */void ixNpeMhConfigUninit (void);/** * @fn void ixNpeMhConfigIsrRegister (           IxNpeMhNpeId npeId,           IxNpeMhConfigIsr isr) * * @brief This function registers an ISR to handle NPE "outFIFO not * empty" interrupts. * * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will * be handled. * @param IxNpeMhConfigIsr isr (in) - the ISR function pointer that the * interrupt will trigger. * * @return No return value. */void ixNpeMhConfigIsrRegister (    IxNpeMhNpeId npeId,    IxNpeMhConfigIsr isr);/** * @fn BOOL ixNpeMhConfigNpeInterruptEnable (           IxNpeMhNpeId npeId) * * @brief This function enables a NPE's "outFIFO not empty" interrupt. * * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will * be enabled. * * @return Returns the previous state of the interrupt (TRUE => enabled). */BOOL ixNpeMhConfigNpeInterruptEnable (    IxNpeMhNpeId npeId);/** * @fn BOOL ixNpeMhConfigNpeInterruptDisable (           IxNpeMhNpeId npeId) * * @brief This function disables a NPE's "outFIFO not empty" interrupt * * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will * be disabled. * * @return Returns the previous state of the interrupt (TRUE => enabled). */BOOL ixNpeMhConfigNpeInterruptDisable (    IxNpeMhNpeId npeId);/** * @fn IxNpeMhMessageId ixNpeMhConfigMessageIdGet (           IxNpeMhMessage message) * * @brief This function gets the ID of a message.