?? lpc24xx.h
字號:
/* Reset, reset source identification */
#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))
/* RSID, code security protection */
#define CSPR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184))
/* AHB configuration */
#define AHBCFG1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188))
#define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C))
/* System Controls and Status */
#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))
/* External Memory Controller (EMC) */
#define EMC_BASE_ADDR 0xFFE08000
#define EMCControl (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000))
#define EMCStatus (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004))
#define EMCConfig (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008))
/* Static Dynamic RAM access registers */
#define EMCDynamicControl (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020))
#define EMCDynamicRefresh (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024))
#define EMCDynamicReadConfig (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028))
#define EMCDynamictRP (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030))
#define EMCDynamictRAS (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034))
#define EMCDynamictSREX (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038))
#define EMCDynamictAPR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C))
#define EMCDynamictDAL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040))
#define EMCDynamictRC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048))
#define EMCDynamictRFC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C))
#define EMCDynamictXSR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050))
#define EMCDynamictRRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054))
#define EMCDynamictMRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058))
#define EMCDynamicConfig0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100))
#define EMCDynamicContro1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x120))
#define EMCDynamicContro2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140))
#define EMCDynamicContro3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160))
#define EMCDynamicRASCAS0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104))
#define EMCDynamicRASCAS1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x124))
#define EMCDynamicRASCAS2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144))
#define EMCDynamicRASCAS3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164))
/* Static RAM access registers */
#define EMCStaticConfig0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200))
#define EMCStaticWaitWen0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204))
#define EMCStaticWaitOen0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208))
#define EMCStaticWaitRd0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C))
#define EMCStaticWaitPage0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210))
#define EMCStaticWaitWr0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214))
#define EMCStaticWaitTurn0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218))
#define EMCStaticConfig1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220))
#define EMCStaticWaitWen1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224))
#define EMCStaticWaitOen1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228))
#define EMCStaticWaitRd1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C))
#define EMCStaticWaitPage1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230))
#define EMCStaticWaitWr1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234))
#define EMCStaticWaitTurn1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238))
#define EMCStaticExtendedWait (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880))
#define EMCStaticConfig2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240))
#define EMCStaticWaitWen2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244))
#define EMCStaticWaitOen2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248))
#define EMCStaticWaitRd2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C))
#define EMCStaticWaitPage2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250))
#define EMCStaticWaitWr2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254))
#define EMCStaticWaitTurn2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258))
#define EMCStaticConfig3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260))
#define EMCStaticWaitWen3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264))
#define EMCStaticWaitOen3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268))
#define EMCStaticWaitRd3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C))
#define EMCStaticWaitPage3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270))
#define EMCStaticWaitWr3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274))
#define EMCStaticWaitTurn3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278))
#define EMCStaticExtendedWait (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880))
/* Timer 0 */
#define TMR0_BASE_ADDR 0xE0004000
#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
#define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))
#define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))
#define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))
#define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))
#define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))
#define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))
#define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))
#define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))
#define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))
#define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))
#define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34))
#define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38))
#define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))
#define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))
/* Timer 1 */
#define TMR1_BASE_ADDR 0xE0008000
#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
#define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))
#define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))
#define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))
#define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))
#define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))
#define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))
#define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))
#define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))
#define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))
#define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30))
#define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34))
#define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38))
#define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C))
#define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))
/* Timer 2 */
#define TMR2_BASE_ADDR 0xE0070000
#define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00))
#define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04))
#define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08))
#define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C))
#define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10))
#define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14))
#define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18))
#define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C))
#define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20))
#define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24))
#define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28))
#define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C))
#define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30))
#define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34))
#define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38))
#define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C))
#define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70))
/* Timer 3 */
#define TMR3_BASE_ADDR 0xE0074000
#define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00))
#define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04))
#define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08))
#define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C))
#define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10))
#define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14))
#define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18))
#define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C))
#define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20))
#define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24))
#define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28))
#define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C))
#define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30))
#define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34))
#define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38))
#define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C))
#define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70))
/* Pulse Width Modulator (PWM) */
/*
#define PWM0_BASE_ADDR 0xE0014000
#define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00))
#define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04))
#define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08))
#define PWM0PR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C))
#define PWM0PC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10))
#define PWM0MCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14))
#define PWM0MR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18))
#define PWM0MR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C))
#define PWM0MR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20))
#define PWM0MR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24))
#define PWM0CCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28))
#define PWM0CR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C))
#define PWM0CR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30))
#define PWM0CR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x34))
#define PWM0CR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x38))
#define PWM0EMR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x3C))
#define PWM0MR4 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40))
#define PWM0MR5 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44))
#define PWM0MR6 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48))
#define PWM0PCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C))
#define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50))
#define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70))
*/
#define PWM1_BASE_ADDR 0xE0018000
#define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00))
#define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04))
#define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08))
#define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C))
#define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10))
#define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14))
#define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18))
#define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C))
#define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20))
#define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24))
#define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28))
#define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C))
#define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30))
#define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34))
#define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38))
#define PWM1EMR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C))
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