#IFNDEF __RELPC932_H
#DEFINE __RELPC932_H

//BYTE Register

sfr     ACC          = 0xE0;
sfr     AUXR1        = 0xA2;
sfr     B            = 0xF0;
sfr     BRGR0        = 0xBE;
sfr       BRGR1        = 0xBF;
sfr    BRGCON       = 0xBD;
sfr    CCCRA        = 0xEA;
sfr    CCCRB        = 0xEB;
sfr    CCCRC        = 0xEC;
sfr    CCCRD        = 0xED;
sfr    CMP1         = 0xAC;
sfr    CMP2         = 0xAD;
sfr    DEECON       = 0xF1;
sfr    DEEDAT       = 0xF2;
sfr    DEEADR       = 0xF3;
sfr    DIVM         = 0x95;
sfr    DPH           = 0x83;
sfr    DPL           = 0x82;
sfr    FMADRH       = 0xE7;
sfr    FMADRL       = 0xE6;
sfr    FMCON        = 0xE4;
sfr    FMDATA       = 0xE5;
sfr    I2ADR        = 0xDB;
sfr    I2CON       = 0xD8;
sfr    I2DAT        = 0xDA;
sfr    I2SCL        = 0xDD;
sfr    I2SCLL       = 0xDC;
sfr    I2STAT       = 0xD9;
sfr    ICRAH        = 0xAB;
sfr    ICRAL        = 0xAA;
sfr    ICRBH         = 0xAF;
sfr    ICRBL        = 0xAE;
sfr    IEN0         = 0xA8;
sfr    IEN1        = 0xE8;
sfr    IP0          = 0xB8;
sfr    IP0H         = 0xB7;
sfr    IP1         = 0xF8;
sfr    IP1H         = 0xF7;
sfr    KBCON        = 0x94;
sfr    KBMASK       = 0x86;
sfr    KBPATN       = 0x93;
sfr    OCRAH       = 0xEF;
sfr    OCRAL        = 0xEE;
sfr    OCRBH        = 0xFB;
sfr    OCRBL        = 0xFA;
sfr    OCRCH        = 0xFD;
sfr    OCRCL        = 0xFC;
sfr    OCRDH        = 0xFF;
sfr    OCRDL        = 0xFE;
sfr    P0           = 0x80;
sfr    P1           = 0x90;
sfr    P2           = 0xA0;
sfr    P3           = 0xB0;
sfr    P0M1         = 0x84;
sfr    P0M2         = 0x85;
sfr    P1M1         = 0x91;
sfr    P1M2         = 0x92;
sfr    P2M1         = 0xA4;
sfr    P2M2         = 0xA5;
sfr    P3M1         = 0xB1;
sfr    P3M2         = 0xB2;
sfr    PCON         = 0x87;
sfr    PCONA        = 0xB5;
sfr    PCONB        = 0xB6;
sfr    PSW          = 0xD0;
sfr    PT0AD        = 0xF6;
sfr    RSTSRC       = 0xDF;
sfr    RTCCON       = 0xD1;
sfr    RTCH         = 0xD2;
sfr    RTCL         = 0xD3;
sfr    SADDR        = 0xA9;
sfr    SADEN        = 0xB9;
sfr    SBUF          = 0x99;
sfr    SCON         = 0x98;
sfr    SSTAT        = 0xBA;
sfr    SP            = 0x81;
sfr    SPCTL        = 0xE2;
sfr    SPSTATSPI    = 0xE1;
sfr    SPDAT        = 0xE3;
sfr    TAMOD        = 0x8F;
sfr    TCON         = 0x88;
sfr    TCR20       = 0xC8;
sfr    TCR21        = 0xF9;
sfr    TH0           = 0x8C;
sfr    TH1           = 0x8D;
sfr    TH2          = 0xCD;
sfr    TICR2        = 0xC9;
sfr    TIFR2        = 0xE9;
sfr    TISE2        = 0xDE;
sfr    TL0           = 0x8A;
sfr    TL1           = 0x8B;
sfr    TL2          = 0xCC;
sfr    TMOD          = 0x89;
sfr    TOR2H        = 0xCF;
sfr    TOR2L        = 0xCE;
sfr    TPCR2HPrescal= 0xCB;
sfr    TPCR2L       = 0xCA;
sfr    TRIM         = 0x96;
sfr    WDCON        = 0xA7;
sfr    WDL          = 0xC1;
sfr    WFEED1       = 0xC2;
sfr    WFEED2       = 0xC3;

//Bit Register
/*  PSW   */
at 0xD7 sbit CY   ;
at 0xD6 sbit AC   ;
at 0xD5 sbit F0   ;
at 0xD4 sbit RS1  ;
at 0xD3 sbit RS0  ;
at 0xD2 sbit OV   ;
at 0xD1 sbit F1	;
at 0xD0 sbit P    ;

/*  TCON  */
at 0x8F sbit TF1  ;
at 0x8E sbit TR1  ;
at 0x8D sbit TF0  ;
at 0x8C sbit TR0  ;
at 0x8B sbit IE1  ;
at 0x8A sbit IT1  ;
at 0x89 sbit IE0  ;
at 0x88 sbit IT0  ;

/*  IEN0  */
at 0xAF sbit EA   ;
at 0xAE sbit EWDRT  ;
at 0xAD sbit EB0  ;
at 0xAC sbit ES   ;
at 0xAB sbit ET1  ;
at 0xAA sbit EX1  ;
at 0xA9 sbit ET0  ;
at 0xA8 sbit EX0  ;

/*  IEN1  */
at 0xEF sbit EIEE ;
at 0xEE sbit EST	;
at 0xEC sbit ECCU ;
at 0xEB sbit ESPI ;
at 0xEA sbit EC   ;
at 0xE9 sbit EKBI ;
at 0xE8 sbit EI2C ;

/*  IP0  */
at 0xBE sbit PWDRT;
at 0xBD sbit PB0  ;
at 0xBC sbit PS   ;
at 0xBB sbit PT1  ;
at 0xBA sbit PX1  ;
at 0xB9 sbit PT0  ;
at 0xB8 sbit PX0  ;

/*  IP1  */
at 0xFF sbit PIEE  ;
at 0xFE sbit PST  ;
at 0xFC sbit PCCU ;
at 0xFB sbit PSPI ;
at 0xFA sbit PC   ;
at 0xF9 sbit PKBI  ;
at 0xF8 sbit PI2C  ;

/*  P0  */
at 0x87 sbit T1;
at 0x87 sbit KB7;
at 0x87 sbit P07;
at 0x86 sbit ICA;
at 0x86 sbit KB6;
at 0x86 sbit P06;
at 0x85 sbit OCA;
at 0x85 sbit KB5;
at 0x85 sbit P05;
at 0x84 sbit CMPREF;
at 0x84 sbit KB4;
at 0x84 sbit P04;
at 0x83 sbit CIN1A;
at 0x83 sbit KB3;
at 0x83 sbit P03;
at 0x82 sbit CIN1B;
at 0x82 sbit KB2;
at 0x82 sbit P02;
at 0x81 sbit CIN2A;
at 0x81 sbit KB1;
at 0x81 sbit P01;
at 0x80 sbit CIN2B;
at 0x80 sbit KB0;
at 0x80 sbit P00;

/*  P1  */
at 0x97 sbit OCC ;
at 0x97 sbit P17 ;
at 0x96 sbit OCB ;
at 0x96 sbit P16 ;
at 0x95 sbit RST ;
at 0x95 sbit P15 ;
at 0x94 sbit INT1 ;
at 0x94 sbit P14 ;
at 0x93 sbit INT0 ;
at 0x93 sbit SDA ;
at 0x93 sbit P13 ;
at 0x92 sbit T0  ;
at 0x92 sbit SCL  ;
at 0x92 sbit P12  ;
at 0x91 sbit RXD  ;
at 0x91 sbit P11  ;
at 0x90 sbit TXD  ;
at 0x90 sbit P10  ;


/*  SCON  */
at 0x9F sbit SM0  ;      
at 0x9E sbit SM1  ;
at 0x9D sbit SM2  ;
at 0x9C sbit REN  ;
at 0x9B sbit TB8  ;
at 0x9A sbit RB8  ;
at 0x99 sbit TI   ;
at 0x98 sbit RI   ;
at 0x9F sbit FE   ;
          
/*  I2CFG  */
at 0xCF sbit SLAVEN;
at 0xCE sbit MASTRQ;
at 0xCD sbit CLRTI ;
at 0xCC sbit TIRUN ;
at 0xC9 sbit CT1   ;
at 0xC8 sbit CT0   ;

/*  I2CON  */
at 0xDF sbit RDAT  ;
at 0xDF sbit CXA   ;
at 0xDE sbit ATN   ;
at 0xDE sbit IDLE  ;
at 0xDD sbit DRDY  ;
at 0xDD sbit CDR   ;
at 0xDC sbit ARL   ;
at 0xDC sbit CARL  ;
at 0xDB sbit STR   ;
at 0xDB sbit CSTR  ;
at 0xDA sbit STP   ;
at 0xDA sbit CSTP  ;
at 0xD9 sbit MASTER;
at 0xD9 sbit XSTR  ;
at 0xD8 sbit XSTP  ;


//I2CCON
sbit 	I2EN		=	0xDE;
sbit 	STA		=	0xDD;
sbit	STO		=	0xDC;
sbit 	SI			=	0xDB;
sbit 	AA			=	0xDA;
sbit 	CRSEL		=	0xD8;

//P2
at 0xA0	sbit  P20;
at 0xA1	sbit	P21;
at 0xA2	sbit 	P22;
at 0xA3	sbit	P23;
at 0xA4	sbit	P24;
at 0xA5	sbit	P25;
at 0xA6	sbit	P26;
at 0xA7	sbit	P27;

//P3
at 0xB0	sbit  P30;
at 0xB1	sbit	P31;
at 0xB2	sbit 	P32;
at 0xB3	sbit	P33;
at 0xB4	sbit	P34;
at 0xB5	sbit	P35;
at 0xB6	sbit	P36;
at 0xB7	sbit	P37;



#ENDIF