module admodule(clk,reset,busy,ad_date,cs,ad_rd,dpram_we,dpram_addr,
                dpram_data,int_to_pc104
    );
	 input clk,reset,busy;
	 input [15:0] ad_date;
	 output ad_rd,dpram_we,int_to_pc104;
	 output [3:0] cs;
	 output [15:0] dpram_addr,dpram_data;
	 reg ad_rd,dpram_we,int_to_pc104;
	 reg [3:0] cs;
	 reg [15:0] dpram_addr,dpram_data;
	 reg [2:0] adcnt;
	 reg [2:0] channelcnt;
	 reg [4:0] icount;
	 reg [7:0] busy_cnt_ent;
	 reg [9:0] samcnt;
	 reg [15:0] sreg_ad,next_sreg_ad;
	 wire flag_busy;
	 wire [15:0] ad_dpram_addr;
	 parameter DCMD_RUN_INT1=16'h0101,DCMD_RUN_INT2=16'h0102,
	           DCMD_RUN_INT3=16'h0103,DCMD_RUN_INT4=16'h0104,
				  DBASE_ADDR=16'h0800,PACKET_LEN=11'b10000000000,
				  ST0=4'd0,ST1=4'd1,ST2=4'd2,ST3=4'd3,ST4=4'd4,
				  ST5=4'd5,ST6=4'd6,ST7=4'd7,ST8=4'd8,ST9=4'd9,
				  ST10=4'd10,ST11=4'd11,ST12=4'd12,ST13=4'd13,
				  ST14=4'd14,ST15=4'd15,FPGA_ADDR_CMD=16'h7FFF;
	 integer i;
	always @(posedge clk)
	  begin
		 if (reset) 
		   busy_cnt_ent<=0;
		 else 
		   busy_cnt_ent<={busy_cnt_ent[6:0],busy};
	  end
	
   assign flag_busy=(busy_cnt_ent==8'hf0);	
	
	always @(posedge clk or posedge reset)
	  if (reset) 
		  begin 
		    sreg_ad<=0;
	       sreg_ad[ST0]<=1'b1;
		  end
		else
		    sreg_ad<=next_sreg_ad;
	
	always @(sreg_ad or flag_busy or adcnt or channelcnt or samcnt)
	   begin
		  next_sreg_ad=16'b0;
	       case(1'b1)
			  sreg_ad[ST0]:
			    if(flag_busy)
			      next_sreg_ad[ST1]=1'b1;
				 else
				   next_sreg_ad[ST0]=1'b1;
			  sreg_ad[ST1]:
			    next_sreg_ad[ST2]=1'b1;
			  sreg_ad[ST2]:
			    next_sreg_ad[ST3]=1'b1;
			  sreg_ad[ST3]:
			    next_sreg_ad[ST4]=1'b1;
			  sreg_ad[ST4]:
			    next_sreg_ad[ST5]=1'b1;
			  sreg_ad[ST5]:
			    next_sreg_ad[ST6]=1'b1;
			  sreg_ad[ST6]:
			    if(channelcnt<=5)
				   next_sreg_ad[ST2]=1'b1;
				 else
				   next_sreg_ad[ST7]=1'b1;
			  sreg_ad[ST7]:
			    next_sreg_ad[ST8]=1'b1;
			  sreg_ad[ST8]:
				 if(adcnt<=3)
				   next_sreg_ad[ST1]=1'b1;
				 else
				   next_sreg_ad[ST9]=1'b1;
			  sreg_ad[ST9]:
			    next_sreg_ad[ST10]=1'b1;
           sreg_ad[ST10]:
			    case(samcnt)
				   255:   next_sreg_ad[ST11]=1'b1;
					511:   next_sreg_ad[ST12]=1'b1;
	            767:   next_sreg_ad[ST13]=1'b1;
					1023:  next_sreg_ad[ST14]=1'b1;
				 default: next_sreg_ad[ST0]=1'b1;
				 endcase
			  sreg_ad[ST11]:
			    next_sreg_ad[ST15]=1'b1;
			  sreg_ad[ST12]:
			    next_sreg_ad[ST15]=1'b1;
			  sreg_ad[ST13]:
			    next_sreg_ad[ST15]=1'b1;
			  sreg_ad[ST14]:
			    next_sreg_ad[ST15]=1'b1;
			  sreg_ad[ST15]:
			    next_sreg_ad[ST0]=1'b1;
			  default:
			    next_sreg_ad[ST0]=1'b1;
			  endcase
			end
			
	always @(posedge clk or posedge reset)
	  if(reset)
	    ad_rd<=1;
	  else if(next_sreg_ad[ST2]|next_sreg_ad[ST3]|
	          next_sreg_ad[ST4]|next_sreg_ad[ST5]==1)
		 ad_rd<=0;
	  else
	    ad_rd<=1;
	
	always @(posedge clk or posedge reset)
	  if(reset)
	    dpram_we<=0;
	  else if(next_sreg_ad[ST5]|next_sreg_ad[ST11]|
	          next_sreg_ad[ST12]|next_sreg_ad[ST13]|
				 next_sreg_ad[ST14]==1)
		 dpram_we<=1;
	  else
	    dpram_we<=0;
		 
	always @(posedge clk or posedge reset)
	  if(reset)
	    int_to_pc104<=0;
	  else if(next_sreg_ad[ST15]==1)
	    int_to_pc104<=1;
	  else
	    int_to_pc104<=0;
		 
	always @(posedge clk or posedge reset)
	  if(reset)
	    cs<=4'b1111;
	  else if(next_sreg_ad[ST1]==1)
	    for(i=3;i>=0;i=i-1)
	      cs[i]<=(i==adcnt)?'b0:'b1;
	  else if(next_sreg_ad[ST9]==1)
	    cs<=4'b1111;
	
	always @(posedge clk or posedge reset)
	  if(reset)
	    dpram_addr<=0;
	  else if(next_sreg_ad[ST5]==1)
	    dpram_addr<=ad_dpram_addr;
	  else if(next_sreg_ad[ST11]|next_sreg_ad[ST12]|
	          next_sreg_ad[ST13]|next_sreg_ad[ST14]==1'b1)
	    dpram_addr<=FPGA_ADDR_CMD;
	  else
	    dpram_addr<=0;
	
	always @(posedge clk or posedge reset)
	  if(reset)
	    dpram_data<=0;
	  else if(next_sreg_ad[ST5]==1)
	    dpram_data<=ad_date;
	  else if(next_sreg_ad[ST11]==1)
	    dpram_data<=DCMD_RUN_INT1;
	  else if(next_sreg_ad[ST12]==1)
	    dpram_data<=DCMD_RUN_INT2; 
	  else if(next_sreg_ad[ST13]==1)
	    dpram_data<=DCMD_RUN_INT3;
	  else if(next_sreg_ad[ST14]==1)
	    dpram_data<=DCMD_RUN_INT4;
	  else 
	    dpram_data<=0;
	
	always @(posedge clk or posedge reset)
	  if(reset)
	    adcnt<=0;
	  else if(next_sreg_ad[ST7]==1)
	    adcnt<=adcnt+1;
	  else if(next_sreg_ad[ST9]==1)
	    adcnt<=0;
	
	always @(posedge clk or posedge reset)
	  if(reset)
	    channelcnt<=0;
	  else if(next_sreg_ad[ST5]==1)
	    channelcnt<=channelcnt+1;
	  else if(next_sreg_ad[ST7]==1)
	    channelcnt<=0;
		 
	always @(posedge clk or posedge reset)
	  if(reset)
	    samcnt<=0;
	  else if(next_sreg_ad[ST9]==1)
	    samcnt<=samcnt+1;
	
	always @(posedge clk or posedge reset)
	  if(reset)
	    icount<=0;
	  else if(next_sreg_ad[ST6]==1)
	    icount<=icount+1;
	  else if(next_sreg_ad[ST9]==1)
	    icount<=0;
	
	assign ad_dpram_addr=DBASE_ADDR+PACKET_LEN*icount+samcnt;
	  
endmodule