library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity bl is
    port (
        BLCLK: in STD_LOGIC;
        reset :in std_logic;
        output: out STD_LOGIC
      --  output1: out STD_LOGIC
    );
end bl;
architecture behave of bl is
begin   
  -- <<enter your statements here>>    
    P1:process(BLCLK)             
    begin            
       if BLCLK'event and BLCLK='0'  then           
           if (reset='1')  then
                output<='0';
           else 
                output<='1';
           end if;        
        end if;  
     --  output1<=output ;	 
    end process;           
end behave;