library IEEE;
use IEEE.std_logic_1164.all;

entity cout8 is
port (
		RUNDIR:  in STD_LOGIC_VECTOR (2 downto 0);
        OUTADD :  out STD_LOGIC_VECTOR (3 downto 0)
    );
end entity cout8;
architecture behave of cout8 is
begin
 P1:process(RUNDIR)
 begin
  		case RUNDIR is
  				when "000" => OUTADD<=2;
                when "001" => OUTADD<=6;  
				when "010" => OUTADD<=4; 
                when "011" => OUTADD<=5;  
                when "100" => OUTADD<=1; 
				when "101" => OUTADD<=9; 
                when "110" => OUTADD<=8;  
                when others =>OUTADD<=10;  
        	end case;
end process;
end behave;