library IEEE;
use IEEE.std_logic_1164.all;

entity  cout8 is
port (
		RUNDIR:  in STD_LOGIC_VECTOR (2 downto 0);
        ADDS:    OUT  STD_LOGIC_VECTOR (3 downto 0)
    );
end entity cout8;
architecture behave of cout8 is

begin
process(RUNDIR)
 -- variable  out_temp : STD_LOGIC_VECTOR (3 downto 0) ; 
  begin
    case RUNDIR is     
   when "000" => ADDS<="0010";
   when "001" => ADDS<="0110";
   when "010" => ADDS<="0100";
   when "011" => ADDS<="0101";
   when "100" => ADDS<="0001";
   when "101" => ADDS<="1001"; 
   when "110" => ADDS<="1000";
   when others => ADDS<="1010";
  end case;

end Process ;
end behave;