?? xxout.vhd
字號:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity xxout is
port (
clk:in std_logic;
flag: buffer STD_LOGIC
);
end xxout;
architecture behave of xxout is
begin
-- <<enter your statements here>>
P1:process(clk)
variable first :std_logic;
begin
if clk'event and clk='1' then
if (first='0') then
flag<='0';
first:='1';
else
flag<='1';
end if;
end if;
end process;
end behave;
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