library IEEE;
use IEEE.std_logic_1164.all;
entity delay is
    port (
          INADDRESS : IN STD_LOGIC_VECTOR (5 downto 0);
		  OUTADDRESS : OUT STD_LOGIC_VECTOR (5 downto 0)
    );
end cout40;
architecture behave of delay is
begin
process(INADDRESS)
 wait for 100 ns;
 INADDRESS<=OUTADDRESS;
end begin;
  end process;       
end behave