?? startup.lst
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ARM GAS Startup.s page 1 1 #/***********************************************************************/ 2 #/* This file is part of the uVision/ARM development tools */ 3 #/* Copyright KEIL ELEKTRONIK GmbH 2002-2004 */ 4 #/***********************************************************************/ 5 #/* */ 6 #/* STARTUP.S: Startup file */ 7 #/* */ 8 #/***********************************************************************/ 9 10 11 /* 12 //*** <<< Use Configuration Wizard in Context Menu >>> *** 13 */ 14 15 16 # *** Startup Code (executed after Reset) *** 17 18 19 # Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs 20 21 .equ Mode_USR, 0x10 22 .equ Mode_FIQ, 0x11 23 .equ Mode_IRQ, 0x12 24 .equ Mode_SVC, 0x13 25 .equ Mode_ABT, 0x17 26 .equ Mode_UND, 0x1B 27 .equ Mode_SYS, 0x1F 28 29 .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ 30 .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ 31 32 33 /* 34 // <h> Stack Configuration 35 // <o> Top of Stack Address <0x0-0xFFFFFFFF:4> 36 // <h> Stack Sizes (in Bytes) 37 // <o1> Undefined Mode <0x0-0xFFFFFFFF:4> 38 // <o2> Supervisor Mode <0x0-0xFFFFFFFF:4> 39 // <o3> Abort Mode <0x0-0xFFFFFFFF:4> 40 // <o4> Fast Interrupt Mode <0x0-0xFFFFFFFF:4> 41 // <o5> Interrupt Mode <0x0-0xFFFFFFFF:4> 42 // <o6> User/System Mode <0x0-0xFFFFFFFF:4> 43 // </h> 44 // </h> 45 */ 46 .equ Top_Stack, 0x40004000 47 .equ UND_Stack_Size, 0x00000004 48 .equ SVC_Stack_Size, 0x00000004 49 .equ ABT_Stack_Size, 0x00000004 50 .equ FIQ_Stack_Size, 0x00000004 51 .equ IRQ_Stack_Size, 0x00000080 52 .equ USR_Stack_Size, 0x00000400 53 54 55 # VPBDIV definitions 56 .equ VPBDIV, 0xE01FC100 /* VPBDIV Address */ 57 ARM GAS Startup.s page 2 58 /* 59 // <e> VPBDIV Setup 60 // <i> Peripheral Bus Clock Rate 61 // <o1.0..1> VPBDIV: VPB Clock 62 // <0=> VPB Clock = CPU Clock / 4 63 // <1=> VPB Clock = CPU Clock 64 // <2=> VPB Clock = CPU Clock / 2 65 // <o1.4..5> XCLKDIV: XCLK Pin 66 // <0=> XCLK Pin = CPU Clock / 4 67 // <1=> XCLK Pin = CPU Clock 68 // <2=> XCLK Pin = CPU Clock / 2 69 // </e> 70 */ 71 .equ VPBDIV_SETUP, 0 72 .equ VPBDIV_Val, 0x00000000 73 74 75 # Phase Locked Loop (PLL) definitions 76 .equ PLL_BASE, 0xE01FC080 /* PLL Base Address */ 77 .equ PLLCON_OFS, 0x00 /* PLL Control Offset*/ 78 .equ PLLCFG_OFS, 0x04 /* PLL Configuration Offset */ 79 .equ PLLSTAT_OFS, 0x08 /* PLL Status Offset */ 80 .equ PLLFEED_OFS, 0x0C /* PLL Feed Offset */ 81 .equ PLLCON_PLLE, (1<<0) /* PLL Enable */ 82 .equ PLLCON_PLLC, (1<<1) /* PLL Connect */ 83 .equ PLLCFG_MSEL, (0x1F<<0) /* PLL Multiplier */ 84 .equ PLLCFG_PSEL, (0x03<<5) /* PLL Divider */ 85 .equ PLLSTAT_PLOCK, (1<<10) /* PLL Lock Status */ 86 87 /* 88 // <e> PLL Setup 89 // <o1.0..4> MSEL: PLL Multiplier Selection 90 // <1-32><#-1> 91 // <i> M Value 92 // <o1.5..6> PSEL: PLL Divider Selection 93 // <0=> 1 <1=> 2 <2=> 4 <3=> 8 94 // <i> P Value 95 // </e> 96 */ 97 .equ PLL_SETUP, 1 98 .equ PLLCFG_Val, 0x00000024 99 100 101 # Memory Accelerator Module (MAM) definitions 102 .equ MAM_BASE, 0xE01FC000 /* MAM Base Address */ 103 .equ MAMCR_OFS, 0x00 /* MAM Control Offset*/ 104 .equ MAMTIM_OFS, 0x04 /* MAM Timing Offset */ 105 106 /* 107 // <e> MAM Setup 108 // <o1.0..1> MAM Control 109 // <0=> Disabled 110 // <1=> Partially Enabled 111 // <2=> Fully Enabled 112 // <i> Mode 113 // <o2.0..2> MAM Timing 114 // <0=> Reserved <1=> 1 <2=> 2 <3=> 3 ARM GAS Startup.s page 3 115 // <4=> 4 <5=> 5 <6=> 6 <7=> 7 116 // <i> Fetch Cycles 117 // </e> 118 */ 119 .equ MAM_SETUP, 1 120 .equ MAMCR_Val, 0x00000002 121 .equ MAMTIM_Val, 0x00000004 122 123 124 # External Memory Controller (EMC) definitions 125 .equ EMC_BASE, 0xFFE00000 /* EMC Base Address */ 126 .equ BCFG0_OFS, 0x00 /* BCFG0 Offset */ 127 .equ BCFG1_OFS, 0x04 /* BCFG1 Offset */ 128 .equ BCFG2_OFS, 0x08 /* BCFG2 Offset */ 129 .equ BCFG3_OFS, 0x0C /* BCFG3 Offset */ 130 131 /* 132 // <e> External Memory Controller (EMC) 133 */ 134 .equ EMC_SETUP, 0 135 136 /* 137 // <e> Bank Configuration 0 (BCFG0) 138 // <o1.0..3> IDCY: Idle Cycles <0-15> 139 // <o1.5..9> WST1: Wait States 1 <0-31> 140 // <o1.11..15> WST2: Wait States 2 <0-31> 141 // <o1.10> RBLE: Read Byte Lane Enable 142 // <o1.26> WP: Write Protect 143 // <o1.27> BM: Burst ROM 144 // <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit 145 // <2=> 32-bit <3=> Reserved 146 // </e> 147 */ 148 .equ BCFG0_SETUP, 0 149 .equ BCFG0_Val, 0x0000FBEF 150 151 /* 152 // <e> Bank Configuration 1 (BCFG1) 153 // <o1.0..3> IDCY: Idle Cycles <0-15> 154 // <o1.5..9> WST1: Wait States 1 <0-31> 155 // <o1.11..15> WST2: Wait States 2 <0-31> 156 // <o1.10> RBLE: Read Byte Lane Enable 157 // <o1.26> WP: Write Protect 158 // <o1.27> BM: Burst ROM 159 // <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit 160 // <2=> 32-bit <3=> Reserved 161 // </e> 162 */ 163 .equ BCFG1_SETUP, 0 164 .equ BCFG1_Val, 0x0000FBEF 165 166 /* 167 // <e> Bank Configuration 2 (BCFG2) 168 // <o1.0..3> IDCY: Idle Cycles <0-15> 169 // <o1.5..9> WST1: Wait States 1 <0-31> 170 // <o1.11..15> WST2: Wait States 2 <0-31> 171 // <o1.10> RBLE: Read Byte Lane Enable ARM GAS Startup.s page 4 172 // <o1.26> WP: Write Protect 173 // <o1.27> BM: Burst ROM 174 // <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit 175 // <2=> 32-bit <3=> Reserved 176 // </e> 177 */ 178 .equ BCFG2_SETUP, 0 179 .equ BCFG2_Val, 0x0000FBEF 180 181 /* 182 // <e> Bank Configuration 3 (BCFG3) 183 // <o1.0..3> IDCY: Idle Cycles <0-15> 184 // <o1.5..9> WST1: Wait States 1 <0-31> 185 // <o1.11..15> WST2: Wait States 2 <0-31> 186 // <o1.10> RBLE: Read Byte Lane Enable 187 // <o1.26> WP: Write Protect 188 // <o1.27> BM: Burst ROM 189 // <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit 190 // <2=> 32-bit <3=> Reserved 191 // </e> 192 */ 193 .equ BCFG3_SETUP, 0 194 .equ BCFG3_Val, 0x0000FBEF 195 196 /* 197 // </e> End of EMC 198 */ 199 200 201 # External Memory Pins definitions 202 .equ PINSEL2, 0xE002C014 /* PINSEL2 Address */ 203 .equ PINSEL2_Val, 0x0E6149E4 /* CS0..3, OE, WE, BLS0..3, 204 D0..31, A2..23, JTAG Pins */ 205 206 207 # Starupt Code must be linked first at Address at which it expects to run. 208 209 .text 210 .arm 211 212 .global _startup 213 .func _startup 214 _startup: 215 216 217 # Exception Vectors 218 # Mapped to Address 0. 219 # Absolute addressing mode must be used. 220 # Dummy Handlers are implemented as infinite loops which can be modified. 221 222 0000 18F09FE5 Vectors: LDR PC, Reset_Addr 223 0004 18F09FE5 LDR PC, Undef_Addr 224 0008 18F09FE5 LDR PC, SWI_Addr 225 000c 18F09FE5 LDR PC, PAbt_Addr 226 0010 18F09FE5 LDR PC, DAbt_Addr 227 0014 0000A0E1 NOP /* Reserved Vector */ 228 # LDR PC, IRQ_Addr ARM GAS Startup.s page 5 229 0018 F0FF1FE5 LDR PC, [PC, #-0x0FF0] /* Vector from VicVectAddr */ 230 001c 18F09FE5 LDR PC, FIQ_Addr 231 232 0020 58000000 Reset_Addr: .word Reset_Handler 233 0024 40000000 Undef_Addr: .word Undef_Handler 234 0028 44000000 SWI_Addr: .word SWI_Handler 235 002c 48000000 PAbt_Addr: .word PAbt_Handler 236 0030 4C000000 DAbt_Addr: .word DAbt_Handler 237 0034 00000000 .word 0 /* Reserved Address */ 238 0038 50000000 IRQ_Addr: .word IRQ_Handler 239 003c 54000000 FIQ_Addr: .word FIQ_Handler 240 241 0040 0E0000EA Undef_Handler: B Undef_Handler 242 0044 0F0000EA SWI_Handler: B SWI_Handler 243 0048 100000EA PAbt_Handler: B PAbt_Handler 244 004c 110000EA DAbt_Handler: B DAbt_Handler 245 0050 120000EA IRQ_Handler: B IRQ_Handler 246 0054 130000EA FIQ_Handler: B FIQ_Handler 247 ?? 快捷鍵說明
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