248              	 249              	# Reset Handler 250              	 251              	Reset_Handler:   252              	 253              	 254              	.ifdef EXTERNAL_MODE 255              	                LDR     R0, =PINSEL2 256              	                LDR     R1, =PINSEL2_Val 257              	                STR     R1, [R0] 258              	.endif 259              	 260              	 261              	.if EMC_SETUP 262              	                LDR     R0, =EMC_BASE 263              	 264              	.if BCFG0_SETUP 265              	                LDR     R1, =BCFG0_Val 266              	                STR     R1, [R0, #BCFG0_OFS] 267              	.endif 268              	 269              	.if BCFG1_SETUP 270              	                LDR     R1, =BCFG1_Val 271              	                STR     R1, [R0, #BCFG1_OFS] 272              	.endif 273              	 274              	.if BCFG2_SETUP 275              	                LDR     R1, =BCFG2_Val 276              	                STR     R1, [R0, #BCFG2_OFS] 277              	.endif 278              	 279              	.if BCFG3_SETUP 280              	                LDR     R1, =BCFG3_Val 281              	                STR     R1, [R0, #BCFG3_OFS] 282              	.endif 283              	 284              	.endif 285              	ARM GAS  Startup.s 			page 6 286              	 287              	.if VPBDIV_SETUP 288              	                LDR     R0, =VPBDIV 289              	                LDR     R1, =VPBDIV_Val 290              	                STR     R1, [R0] 291              	.endif 292              	 293              	 294              	.if PLL_SETUP 295 0058 D0009FE5 	                LDR     R0, =PLL_BASE 296 005c AA10A0E3 	                MOV     R1, #0xAA 297 0060 5520A0E3 	                MOV     R2, #0x55 298              	 299              	# Configure and Enable PLL 300 0064 2430A0E3 	                MOV     R3, #PLLCFG_Val 301 0068 043080E5 	                STR     R3, [R0, #PLLCFG_OFS]  302 006c 0130A0E3 	                MOV     R3, #PLLCON_PLLE 303 0070 003080E5 	                STR     R3, [R0, #PLLCON_OFS] 304 0074 0C1080E5 	                STR     R1, [R0, #PLLFEED_OFS] 305 0078 0C2080E5 	                STR     R2, [R0, #PLLFEED_OFS] 306              	 307              	# Wait until PLL Locked 308 007c 083090E5 	PLL_Loop:       LDR     R3, [R0, #PLLSTAT_OFS] 309 0080 013B13E2 	                ANDS    R3, R3, #PLLSTAT_PLOCK 310 0084 1D00000A 	                BEQ     PLL_Loop 311              	 312              	# Switch to PLL Clock 313 0088 0330A0E3 	                MOV     R3, #(PLLCON_PLLE | PLLCON_PLLC) 314 008c 003080E5 	                STR     R3, [R0, #PLLCON_OFS] 315 0090 0C1080E5 	                STR     R1, [R0, #PLLFEED_OFS] 316 0094 0C2080E5 	                STR     R2, [R0, #PLLFEED_OFS] 317              	.endif 318              	 319              	 320              	.if MAM_SETUP 321 0098 94009FE5 	                LDR     R0, =MAM_BASE 322 009c 0410A0E3 	                MOV     R1, #MAMTIM_Val 323 00a0 041080E5 	                STR     R1, [R0, #MAMTIM_OFS]  324 00a4 0210A0E3 	                MOV     R1, #MAMCR_Val 325 00a8 001080E5 	                STR     R1, [R0, #MAMCR_OFS]  326              	.endif 327              	 328              	 329              	# Memory Mapping (when Interrupt Vectors are in RAM) 330              	        .equ    MEMMAP, 0xE01FC040  /* Memory Mapping Control */ 331              	         332              	.ifdef RAM_INTVEC 333              	                LDR     R0, =MEMMAP 334              	                MOV     R1, #2 335              	                STR     R1, [R0] 336              	.endif 337              	 338              	 339              	# Initialise Interrupt System 340              	#  ... 341              	 342              	ARM GAS  Startup.s 			page 7 343              	# Setup Stack for each mode 344              	 345 00ac 84009FE5 	                LDR     R0, =Top_Stack 346              	 347              	#  Enter Undefined Instruction Mode and set its Stack Pointer 348 00b0 DBF021E3 	                MSR     CPSR_c, #Mode_UND|I_Bit|F_Bit 349 00b4 00D0A0E1 	                MOV     SP, R0 350 00b8 040040E2 	                SUB     R0, R0, #UND_Stack_Size 351              	 352              	#  Enter Abort Mode and set its Stack Pointer 353 00bc D7F021E3 	                MSR     CPSR_c, #Mode_ABT|I_Bit|F_Bit 354 00c0 00D0A0E1 	                MOV     SP, R0 355 00c4 040040E2 	                SUB     R0, R0, #ABT_Stack_Size 356              	 357              	#  Enter FIQ Mode and set its Stack Pointer 358 00c8 D1F021E3 	                MSR     CPSR_c, #Mode_FIQ|I_Bit|F_Bit 359 00cc 00D0A0E1 	                MOV     SP, R0 360 00d0 040040E2 	                SUB     R0, R0, #FIQ_Stack_Size 361              	 362              	#  Enter IRQ Mode and set its Stack Pointer 363 00d4 D2F021E3 	                MSR     CPSR_c, #Mode_IRQ|I_Bit|F_Bit 364 00d8 00D0A0E1 	                MOV     SP, R0 365 00dc 800040E2 	                SUB     R0, R0, #IRQ_Stack_Size 366              	 367              	#  Enter Supervisor Mode and set its Stack Pointer 368 00e0 D3F021E3 	                MSR     CPSR_c, #Mode_SVC|I_Bit|F_Bit 369 00e4 00D0A0E1 	                MOV     SP, R0 370 00e8 040040E2 	                SUB     R0, R0, #SVC_Stack_Size 371              	 372              	#  Enter User Mode and set its Stack Pointer 373 00ec 10F021E3 	                MSR     CPSR_c, #Mode_USR 374 00f0 00D0A0E1 	                MOV     SP, R0 375              	 376              	#  Setup a default Stack Limit (when compiled with "-mapcs-stack-check") 377 00f4 01AB4DE2 	                SUB     SL, SP, #USR_Stack_Size 378              	 379              	 380              	# Relocate .data section (Copy from ROM to RAM) 381 00f8 3C109FE5 	                LDR     R1, =_etext 382 00fc 3C209FE5 	                LDR     R2, =_data 383 0100 3C309FE5 	                LDR     R3, =_edata 384 0104 030052E1 	LoopRel:        CMP     R2, R3 385 0108 04009134 	                LDRLO   R0, [R1], #4 386 010c 04008234 	                STRLO   R0, [R2], #4 387 0110 3F00003A 	                BLO     LoopRel 388              	 389              	 390              	# Clear .bss section (Zero init) 391 0114 0000A0E3 	                MOV     R0, #0 392 0118 28109FE5 	                LDR     R1, =__bss_start__ 393 011c 28209FE5 	                LDR     R2, =__bss_end__ 394 0120 020051E1 	LoopZI:         CMP     R1, R2 395 0124 04008134 	                STRLO   R0, [R1], #4 396 0128 4600003A 	                BLO     LoopZI 397              	 398              	 399              	# Enter the C codeARM GAS  Startup.s 			page 8 400 012c FEFFFFEA 	                B       _start 401              	 402              	 403              	        .size   _startup, . - _startup 404              	        .endfunc 405              	 406              	 407 0130 80C01FE0 	        .end 407      00C01FE0  407      00400040  407      00000000  407      00000000 ARM GAS  Startup.s 			page 9DEFINED SYMBOLS           Startup.s:21     *ABS*:00000010 Mode_USR           Startup.s:22     *ABS*:00000011 Mode_FIQ           Startup.s:23     *ABS*:00000012 Mode_IRQ           Startup.s:24     *ABS*:00000013 Mode_SVC           Startup.s:25     *ABS*:00000017 Mode_ABT           Startup.s:26     *ABS*:0000001b Mode_UND           Startup.s:27     *ABS*:0000001f Mode_SYS           Startup.s:29     *ABS*:00000080 I_Bit           Startup.s:30     *ABS*:00000040 F_Bit           Startup.s:46     *ABS*:40004000 Top_Stack           Startup.s:47     *ABS*:00000004 UND_Stack_Size           Startup.s:48     *ABS*:00000004 SVC_Stack_Size           Startup.s:49     *ABS*:00000004 ABT_Stack_Size           Startup.s:50     *ABS*:00000004 FIQ_Stack_Size           Startup.s:51     *ABS*:00000080 IRQ_Stack_Size           Startup.s:52     *ABS*:00000400 USR_Stack_Size           Startup.s:56     *ABS*:e01fc100 VPBDIV           Startup.s:71     *ABS*:00000000 VPBDIV_SETUP           Startup.s:72     *ABS*:00000000 VPBDIV_Val           Startup.s:76     *ABS*:e01fc080 PLL_BASE           Startup.s:77     *ABS*:00000000 PLLCON_OFS           Startup.s:78     *ABS*:00000004 PLLCFG_OFS           Startup.s:79     *ABS*:00000008 PLLSTAT_OFS           Startup.s:80     *ABS*:0000000c PLLFEED_OFS           Startup.s:81     *ABS*:00000001 PLLCON_PLLE           Startup.s:82     *ABS*:00000002 PLLCON_PLLC           Startup.s:83     *ABS*:0000001f PLLCFG_MSEL           Startup.s:84     *ABS*:00000060 PLLCFG_PSEL           Startup.s:85     *ABS*:00000400 PLLSTAT_PLOCK           Startup.s:97     *ABS*:00000001 PLL_SETUP           Startup.s:98     *ABS*:00000024 PLLCFG_Val           Startup.s:102    *ABS*:e01fc000 MAM_BASE           Startup.s:103    *ABS*:00000000 MAMCR_OFS           Startup.s:104    *ABS*:00000004 MAMTIM_OFS           Startup.s:119    *ABS*:00000001 MAM_SETUP           Startup.s:120    *ABS*:00000002 MAMCR_Val           Startup.s:121    *ABS*:00000004 MAMTIM_Val           Startup.s:125    *ABS*:ffe00000 EMC_BASE           Startup.s:126    *ABS*:00000000 BCFG0_OFS           Startup.s:127    *ABS*:00000004 BCFG1_OFS           Startup.s:128    *ABS*:00000008 BCFG2_OFS           Startup.s:129    *ABS*:0000000c BCFG3_OFS           Startup.s:134    *ABS*:00000000 EMC_SETUP           Startup.s:148    *ABS*:00000000 BCFG0_SETUP           Startup.s:149    *ABS*:0000fbef BCFG0_Val           Startup.s:163    *ABS*:00000000 BCFG1_SETUP           Startup.s:164    *ABS*:0000fbef BCFG1_Val           Startup.s:178    *ABS*:00000000 BCFG2_SETUP           Startup.s:179    *ABS*:0000fbef BCFG2_Val           Startup.s:193    *ABS*:00000000 BCFG3_SETUP           Startup.s:194    *ABS*:0000fbef BCFG3_Val           Startup.s:202    *ABS*:e002c014 PINSEL2           Startup.s:203    *ABS*:0e6149e4 PINSEL2_Val           Startup.s:214    .text:00000000 _startup           Startup.s:222    .text:00000000 Vectors           Startup.s:232    .text:00000020 Reset_AddrARM GAS  Startup.s 			page 10           Startup.s:233    .text:00000024 Undef_Addr           Startup.s:234    .text:00000028 SWI_Addr           Startup.s:235    .text:0000002c PAbt_Addr           Startup.s:236    .text:00000030 DAbt_Addr           Startup.s:239    .text:0000003c FIQ_Addr           Startup.s:251    .text:00000058 Reset_Handler           Startup.s:241    .text:00000040 Undef_Handler           Startup.s:242    .text:00000044 SWI_Handler           Startup.s:243    .text:00000048 PAbt_Handler           Startup.s:244    .text:0000004c DAbt_Handler           Startup.s:238    .text:00000038 IRQ_Addr           Startup.s:245    .text:00000050 IRQ_Handler           Startup.s:246    .text:00000054 FIQ_Handler           Startup.s:308    .text:0000007c PLL_Loop           Startup.s:330    *ABS*:e01fc040 MEMMAP           Startup.s:384    .text:00000104 LoopRel           Startup.s:394    .text:00000120 LoopZIUNDEFINED SYMBOLS_etext_data_edata__bss_start____bss_end___start