/*
 *  Copyright 2007 by Spectrum Digital Incorporated.
 *  All rights reserved. Property of Spectrum Digital Incorporated.
 */

/*
 *  PSC header file
 *
 */

#ifndef PSC_
#define PSC_

#ifdef __cplusplus
extern "C" {
#endif

#include "davincihd.h"

/* ------------------------------------------------------------------------ *
 *  PSC states                                                              *
 * ------------------------------------------------------------------------ */
#define PSC_SWRSTDISABLE        ( 0 )
#define PSC_SYNCRESET           ( 1 )
#define PSC_DISABLE             ( 2 )
#define PSC_ENABLE              ( 3 )

/* ------------------------------------------------------------------------ *
 *  PSC modules                                                             *
 * ------------------------------------------------------------------------ */
#define LPSC_C64X_CPU           1
#define LPSC_HD_VICP0           2
#define LPSC_HD_VICP1           3
#define LPSC_EDMA_CC            4
#define LPSC_EDMA_TC0           5
#define LPSC_EDMA_TC1           6
#define LPSC_EDMA_TC2           7
#define LPSC_EDMA_TC3           8
#define LPSC_USB                9
#define LPSC_ATA                10
#define LPSC_VLYNQ              11
#define LPSC_HPI                12
#define LPSC_PCI                13
#define LPSC_EMAC               14
#define LPSC_GRAPHICSENGINE     15
#define LPSC_VIDEO_PORT_0       16
#define LPSC_VIDEO_PORT_1       17
#define LPSC_STREAM_IO_0        18
#define LPSC_STREAM_IO_1        19
#define LPSC_DDR2_EMIF          20
#define LPSC_EMIFA              21
#define LPSC_MCASP0             22
#define LPSC_MCASP1             23
#define LPSC_CRGEN0             24
#define LPSC_CRGEN1             25
#define LPSC_UART0              26
#define LPSC_UART1              27
#define LPSC_UART2              28
#define LPSC_PWM0               29
#define LPSC_PWM1               30
#define LPSC_I2C                31
#define LPSC_SPI                32
#define LPSC_GPIO               33
#define LPSC_TIMER0             34
#define LPSC_TIMER1             35
#define LPSC_ARM_INTC           45

/* ------------------------------------------------------------------------ *
 *  Power and Sleep Controller ( PSC )                                      *
 * ------------------------------------------------------------------------ */
#define PSC_BASE                0x01c41000
#define PSC_PID                 *( volatile Uint32* )( PSC_BASE + 0x0 )
#define PSC_INTEVAL             *( volatile Uint32* )( PSC_BASE + 0x18 )
#define PSC_PTCMD               *( volatile Uint32* )( PSC_BASE + 0x120 )
#define PSC_PTSTAT              *( volatile Uint32* )( PSC_BASE + 0x128 )
#define PSC_PDSTAT0             *( volatile Uint32* )( PSC_BASE + 0x200 )
#define PSC_PDCTL0              *( volatile Uint32* )( PSC_BASE + 0x300 )
#define PSC_MDSTAT_BASE         ( PSC_BASE + 0x800 )
#define PSC_MDCTL_BASE          ( PSC_BASE + 0xa00 )

/* ------------------------------------------------------------------------ *
 *  Prototypes                                                              *
 * ------------------------------------------------------------------------ */
Int16 DAVINCIHD_PSC_enableAll( );
Int16 DAVINCIHD_PSC_changeState( Uint32 id, Uint16 state );

#ifdef __cplusplus
}
#endif

#endif