/*  ============================================================================ *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005 * *   Use of this software is controlled by the terms and conditions found in the *   license agreement under which this software has been supplied. *   =========================================================================== *//** @file  csl_pllc.h * *  @brief PLLC functional layer API header file * *  Path: \\(CSLPATH)\\ipmodules\\pllc\\src *//** @mainpage PLLC CSL 3.x * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to identify a set of common CSL APIs for * the PLLC module across various devices. The CSL developer is expected to * refer to this document while designing APIs for these modules. Some of the * listed APIs may not be applicable to a given PLLC module. While other cases * this list of APIs may not be sufficient to cover all the features of a * particular PLLC Module. The CSL developer should use his discretion designing * new APIs or extending the existing ones to cover these. * * @subsection aaa Terms and Abbreviations *   -# CSL:  Chip Support Library *   -# API:  Application Programmer Interface * * @subsection References *    -# CSL-001-DES, CSL 3.x Design Specification Document Version 1.02 * *//* ============================================================================= *  Revision History *  =============== *  10-Feb-2004 kpn CSL3X Upgradation. * ============================================================================= */#ifndef _CSL_PLLC_H_#define _CSL_PLLC_H_#ifdef __cplusplusextern "C" {#endif#include <cslr.h>#include <soc.h>#include <csl_error.h>#include <csl_types.h>#include <cslr_pllc.h>/**\defgroup CSL_PLLC_API PLLC   \internal Based on <b>PLLC Spec Rev 3.4 </b>*//**\defgroup CSL_PLLC_DATASTRUCT Data Structures\ingroup CSL_PLLC_API*//**\defgroup CSL_PLLC_DEFINE  Defines\ingroup CSL_PLLC_API*//**\defgroup CSL_PLLC_ENUM  Enumerated Data Types\ingroup CSL_PLLC_API*//**\defgroup CSL_PLLC_FUNCTION  Functions\ingroup CSL_PLLC_API*//*****************************************************************************\          PLLC global macro declarations\*****************************************************************************//** \defgroup CSL_PLLC_STATUS_DEFINE PLL Controller Status *  \ingroup CSL_PLLC_DEFINE * * @{ *//** Set when GO operation (divide-ratio change and *   clock alignment) is in progress */#define CSL_PLLC_STATUS_GO CSL_FMKT (PLLC_PLLSTAT_GOSTAT, INPROG)/** Set when PLL core is locked */#define CSL_PLLC_STATUS_LOCK CSL_FMKT (PLLC_PLLSTAT_LOCK, YES)/** Set when OSCIN/CLKIN is assumed to be stable */#define CSL_PLLC_STATUS_STABLE CSL_FMKT (PLLC_PLLSTAT_STABLE, YES)/**@} *//** \defgroup CSL_PLLC_DCHANGESTAT_DEFINE PLLC Divider Ratio Modified Status *  \ingroup CSL_PLLC_DEFINE * * @{ *//** SYSCLK8 divide ratio is modified */#define CSL_PLLC_DCHANGESTAT_SYS8 CSL_FMKT (PLLC_DCHANGE_SYS8, YES)/** SYSCLK7 divide ratio is modified */#define CSL_PLLC_DCHANGESTAT_SYS7 CSL_FMKT (PLLC_DCHANGE_SYS7, YES)/** SYSCLK6 divide ratio is modified */#define CSL_PLLC_DCHANGESTAT_SYS6 CSL_FMKT (PLLC_DCHANGE_SYS6, YES)/** SYSCLK5 divide ratio is modified */#define CSL_PLLC_DCHANGESTAT_SYS5 CSL_FMKT (PLLC_DCHANGE_SYS5, YES)/** SYSCLK4 divide ratio is modified */#define CSL_PLLC_DCHANGESTAT_SYS4 CSL_FMKT (PLLC_DCHANGE_SYS4, YES)/** SYSCLK3 divide ratio is modified */#define CSL_PLLC_DCHANGESTAT_SYS3 CSL_FMKT (PLLC_DCHANGE_SYS3, YES)/** SYSCLK2 divide ratio is modified */#define CSL_PLLC_DCHANGESTAT_SYS2 CSL_FMKT (PLLC_DCHANGE_SYS2, YES)/** SYSCLK1 divide ratio is modified */#define CSL_PLLC_DCHANGESTAT_SYS1 CSL_FMKT (PLLC_DCHANGE_SYS1, YES)/**@} *//** \defgroup CSL_PLLC_CLKSTAT_DEFINE PLLC Clock Status *  \ingroup CSL_PLLC_DEFINE * * @{ *//** AUXCLK is ON */#define CSL_PLLC_CLKSTAT_AUXON CSL_FMKT (PLLC_CKSTAT_AUXEN, ON)/** OBSCLK is ON */#define CSL_PLLC_CLKSTAT_OBSON CSL_FMKT (PLLC_CKSTAT_OBSEN, ON)/** SYSCLKBP is ON */#define CSL_PLLC_CLKSTAT_BPON CSL_FMKT (PLLC_CKSTAT_BPON, ON)/**@} *//** \defgroup CSL_PLLC_CLKEN_DEFINE PLLC Clock Enable Status *  \ingroup CSL_PLLC_DEFINE * * @{ *//** AUXCLK enable */#define CSL_PLLC_CLKEN_AUXEN CSL_FMKT (PLLC_CKEN_AUXEN, ENABLE)/** OBSCLK enable */#define CSL_PLLC_CLKEN_OBSEN CSL_FMKT (PLLC_CKEN_OBSEN, ENABLE)/**@} *//** \defgroup CSL_PLLC_SYSCLKSTAT_DEFINE PLLC SYSCLK Status *  \ingroup CSL_PLLC_DEFINE * * @{ *//** SYSCLK8 is ON */#define CSL_PLLC_SYSCLKSTAT_SYS8ON CSL_FMKT (PLLC_CKSTAT_SYS8ON, ON)/** SYSCLK7 is ON */#define CSL_PLLC_SYSCLKSTAT_SYS7ON CSL_FMKT (PLLC_CKSTAT_SYS7ON, ON)/** SYSCLK6 is ON */#define CSL_PLLC_SYSCLKSTAT_SYS6ON CSL_FMKT (PLLC_CKSTAT_SYS6ON, ON)/** SYSCLK5 is ON */#define CSL_PLLC_SYSCLKSTAT_SYS5ON CSL_FMKT (PLLC_CKSTAT_SYS5ON, ON)/** SYSCLK4 is ON */#define CSL_PLLC_SYSCLKSTAT_SYS4ON CSL_FMKT (PLLC_CKSTAT_SYS4ON, ON)/** SYSCLK3 is ON */#define CSL_PLLC_SYSCLKSTAT_SYS3ON CSL_FMKT (PLLC_CKSTAT_SYS3ON, ON)/** SYSCLK2 is ON */#define CSL_PLLC_SYSCLKSTAT_SYS2ON CSL_FMKT (PLLC_CKSTAT_SYS2ON, ON)/** SYSCLK1 is ON */#define CSL_PLLC_SYSCLKSTAT_SYS1ON CSL_FMKT (PLLC_CKSTAT_SYS1ON, ON)/**@} *//** \defgroup CSL_PLLC_RESETSTAT_DEFINE PLLC Last Reset Status *  \ingroup CSL_PLLC_DEFINE * * @{ *//** Power On Reset */#define CSL_PLLC_RESETSTAT_POR CSL_FMKT (PLLC_RSTYPE_POR, YES)/** External Warm Reset */#define CSL_PLLC_RESETSTAT_XWRST CSL_FMKT (PLLC_RSTYPE_XWRST, YES)/** Maximum Reset */#define CSL_PLLC_RESETSTAT_MRST CSL_FMKT (PLLC_RSTYPE_MRST, YES)/** System/Chip Reset */#define CSL_PLLC_RESETSTAT_SRST CSL_FMKT (PLLC_RSTYPE_SRST, YES)/**@} *//** \defgroup CSL_PLLC_CTRL_DEFINE PLLC Control Mask *  \ingroup CSL_PLLC_DEFINE * * @{ *//** PreDiv, PLL, and PostDiv are bypassed. SYSCLK *   divided down directly from input reference *   clock refclk */#define CSL_PLLC_CTRL_BYPASS CSL_FMKT (PLLC_PLLCTL_PLLEN, BYPASS)/** PLL is used. SYSCLK divided down from PostDiv *   output */#define CSL_PLLC_CTRL_ENABLE CSL_FMKT (PLLC_PLLCTL_PLLEN, PLL)/** Selected PLL Operational */#define CSL_PLLC_CTRL_OPERATIONAL CSL_FMKT (PLLC_PLLCTL_PLLPWRDN, NO)/** Selected PLL Placed In Power Down State */#define CSL_PLLC_CTRL_POWERDOWN CSL_FMKT (PLLC_PLLCTL_PLLPWRDN, YES)/** PLL Reset Released */#define CSL_PLLC_CTRL_RELEASE_RESET CSL_FMKT (PLLC_PLLCTL_PLLRST, NO)/** PLL Reset Asserted */#define CSL_PLLC_CTRL_RESET CSL_FMKT (PLLC_PLLCTL_PLLRST, YES)/** PLL Disable Released */#define CSL_PLLC_CTRL_RELEASE_DIS CSL_FMKT (PLLC_PLLCTL_PLLDIS, NO)/** PLL Disable Asserted */#define CSL_PLLC_CTRL_ASSERT_DIS CSL_FMKT (PLLC_PLLCTL_PLLRST, YES)/** PLLEN Mux is controlled by PLLCTL.PLLEN. *   pllen_pi is don抰 care */#define CSL_PLLC_CTRL_MUXCTRL_REGBIT CSL_FMKT (PLLC_PLLCTL_PLLENSRC, REGBIT)/** PLLEN Mux is controlled by input pllen_pi. *   PLLCTL.PLLEN is don抰 care */#define CSL_PLLC_CTRL_MUXCTRL_PORT CSL_FMKT (PLLC_PLLCTL_PLLENSRC, PORT)/** PLL A is selected. PLL B is put in power *   down */#define CSL_PLLC_CTRL_SELECT_PLLA CSL_FMKT (PLLC_PLLCTL_PLLSELB, PLLA)/** PLL B is selected. PLL A is put in power *   down */#define CSL_PLLC_CTRL_SELECT_PLLB CSL_FMKT (PLLC_PLLCTL_PLLSELB, PLLB)/** oscin_pi is the reference clock */#define CSL_PLLC_CTRL_SELECT_OSCIN CSL_FMKT (PLLC_PLLCTL_CLKMODE, OSCIN)/** clkin_pi is the reference clock */#define CSL_PLLC_CTRL_SELECT_CLKIN CSL_FMKT (PLLC_PLLCTL_CLKMODE, CLKIN)/** A write of 1 to this bit signifies that the new *   divide ratios in PLLDIV[1:n] are taken into *   account at the nearest possible rising edge to *   phase align the clocks. The actual SYSCLKx to *   be aligned are selected in register ALNCTL */#define CSL_PLLC_CTRL_ALIGN_PHASE (CSL_FMKT (PLLC_PLLCMD_GOSET, SET)<< 16)/** A write of 1 (doesn抰 need to be a transition *   from 0 to 1) to this bit initiates oscillator *   power down command */#define CSL_PLLC_CTRL_OSCPWRDN (CSL_FMKT (PLLC_PLLCMD_OSCPWRDN, SET)<<16)/**@} *//** \defgroup CSL_PLLC_ALIGNCTL_DEFINE PLLC Align Control *  \ingroup CSL_PLLC_DEFINE * * @{ *//** SYSCLK8 needs to be aligned with other clocks *   selected in this register */#define CSL_PLLC_ALIGNCTL_SYSCLK8 CSL_FMKT (PLLC_ALNCTL_ALN8, YES)/** SYSCLK7 needs to be aligned with other clocks *   selected in this register */#define CSL_PLLC_ALIGNCTL_SYSCLK7 CSL_FMKT (PLLC_ALNCTL_ALN7, YES)/** SYSCLK6 needs to be aligned with other clocks *   selected in this register */#define CSL_PLLC_ALIGNCTL_SYSCLK6 CSL_FMKT (PLLC_ALNCTL_ALN6, YES)/** SYSCLK5 needs to be aligned with other clocks *   selected in this register */#define CSL_PLLC_ALIGNCTL_SYSCLK5 CSL_FMKT (PLLC_ALNCTL_ALN5, YES)/** SYSCLK4 needs to be aligned with other clocks *   selected in this register */#define CSL_PLLC_ALIGNCTL_SYSCLK4 CSL_FMKT (PLLC_ALNCTL_ALN4, YES)/** SYSCLK3 needs to be aligned with other clocks *   selected in this register */#define CSL_PLLC_ALIGNCTL_SYSCLK3 CSL_FMKT (PLLC_ALNCTL_ALN3, YES)/** SYSCLK2 needs to be aligned with other clocks *   selected in this register */#define CSL_PLLC_ALIGNCTL_SYSCLK2 CSL_FMKT (PLLC_ALNCTL_ALN2, YES)/** SYSCLK1 needs to be aligned with other clocks *   selected in this register */#define CSL_PLLC_ALIGNCTL_SYSCLK1 CSL_FMKT (PLLC_ALNCTL_ALN1, YES)/**@} *//** \defgroup CSL_PLLC_DIVEN_DEFINE PLLC Divider Enable *  \ingroup CSL_PLLC_DEFINE * * @{ *//** PREDIV enable */#define CSL_PLLC_DIVEN_PREDIV    (1 << 0)/** POSTDIV enable */#define CSL_PLLC_DIVEN_POSTDIV   (1 << 1)/** Oscillator Divider OD1 Enable */#define CSL_PLLC_DIVEN_OSCDIV1   (1 << 2)/** Enable divider D1 for SYSCLK1 */#define CSL_PLLC_DIVEN_PLLDIV1   (1 << 3)/** Enable divider D2 for SYSCLK2 */#define CSL_PLLC_DIVEN_PLLDIV2   (1 << 4)/** Enable divider D3 for SYSCLK3 */#define CSL_PLLC_DIVEN_PLLDIV3   (1 << 5)/** Enable divider D4 for SYSCLK4 */#define CSL_PLLC_DIVEN_PLLDIV4   (1 << 6)/** Enable divider D4 for SYSCLK4 */#define CSL_PLLC_DIVEN_PLLDIV5   (1 << 7)/** Enable divider D6 for SYSCLK6 */#define CSL_PLLC_DIVEN_PLLDIV6   (1 << 8)/** Enable divider D7 for SYSCLK7 */#define CSL_PLLC_DIVEN_PLLDIV7   (1 << 9)/** Enable divider D8 for SYSCLK8 */#define CSL_PLLC_DIVEN_PLLDIV8   (1 << 10)/**@} *//** \defgroup CSL_PLLC_DIVSEL_DEFINE Divider Select for SYSCLKs *  \ingroup CSL_PLLC_DEFINE * * @{ *//** Divider D1 for SYSCLK1 */#define CSL_PLLC_DIVSEL_PLLDIV1     (1)/** Divider D2 for SYSCLK2 */#define CSL_PLLC_DIVSEL_PLLDIV2     (2)/** Divider D3 for SYSCLK3 */#define CSL_PLLC_DIVSEL_PLLDIV3     (3)/** Divider D4 for SYSCLK4 */#define CSL_PLLC_DIVSEL_PLLDIV4     (4)/** Divider D5 for SYSCLK5 */#define CSL_PLLC_DIVSEL_PLLDIV5     (5)/** Divider D6 for SYSCLK6 */#define CSL_PLLC_DIVSEL_PLLDIV6     (6)/** Divider D7 for SYSCLK7 */#define CSL_PLLC_DIVSEL_PLLDIV7     (7)/** Divider D8 for SYSCLK8 */#define CSL_PLLC_DIVSEL_PLLDIV8     (8)/**@} *//**************************************************************************\* PLLC global typedef declarations                                         *\**************************************************************************//** \defgroup CSL_PLLC_RSTDEF_ENUM Reset Definition *  \ingroup CSL_PLLC_ENUM @{*//** \brief  Enums for PLL XWRST pin function */typedef enum {    /** <b>: Normal mode.      *   xwrst_pi_n causes the xwrst_pi_n operation</b>      */    CSL_PLLC_RSTDEF_NORMAL = CSL_PLLC_RSTDEF_XWFUNC_NORM,    /** <b>: Fast mode.      *   xwrst_pi_n causes the system/chip reset operation</b>      */    CSL_PLLC_RSTDEF_FAST = CSL_PLLC_RSTDEF_XWFUNC_FAST} CSL_PllcResetDef;/**@} *//** \defgroup CSL_PLLC_OSCDIVCTL_ENUM Oscillator Divide Control *  \ingroup CSL_PLLC_ENUM @{*//** \brief  Enums for Oscillator divide enable/ disable */typedef enum {    /** <b>: Oscillator Divider OD1 Disable</b> */    CSL_PLLC_OSCDIV_DISABLE = CSL_PLLC_OSCDIV1_OD1EN_DISABLE,    /** <b>: Oscillator Divider OD1 Enable</b> */    CSL_PLLC_OSCDIV_ENABLE = CSL_PLLC_OSCDIV1_OD1EN_ENABLE} CSL_PllcOscDivCtrl;/**@} *//** \defgroup CSL_PLLC_PLLDIVCTL_ENUM PLL Divide Control *  \ingroup CSL_PLLC_ENUM @{*//** \brief  Enums for PLL divide enable/ disable */typedef enum {    /** <b>: PLL Divider Disable</b> */    CSL_PLLC_PLLDIV_DISABLE = 0,    /** <b>: PLL Divider Enable</b> */    CSL_PLLC_PLLDIV_ENABLE = 1} CSL_PllcDivCtrl;/**@} *//** \defgroup CSL_PLLC_CONTROLCMD_ENUM  Control Commands *  \ingroup CSL_PLLC_CONTROL_API@{*//** \brief Enumeration for control commands passed to \a CSL_pllcHwControl() * *  This is the set of commands that are passed to the \a CSL_pllcHwControl() *  with an optional argument type-casted to \a void* . *  The arguments to be passed with each enumeration (if any) are specified *  next to the enumeration */typedef enum {    /** \brief Control PLL based on the bits set in the input argument     *  \param CSL_BitMask32     *  \return CSL_SOK     *  \sa CSL_PLLC_CTRL_DEFINE     */    CSL_PLLC_CMD_PLLCONTROL,    /** \brief Enable the clocks as specified by input  bitmask     *  \param CSL_BitMask32     *  \return CSL_SOK     *  \sa CSL_PLLC_CLKEN_DEFINE     */    CSL_PLLC_CMD_CLOCK_ENABLE,    /** \brief Disable the clocks specified by input bitmask     *  \param CSL_BitMask32     *  \return CSL_SOK     *  \sa CSL_PLLC_CLKEN_DEFINE     */    CSL_PLLC_CMD_CLOCK_DISABLE,    /** \brief Define XWRST pin function     *  \param CSL_PllcResetDef     *  \return CSL_SOK     *  \sa CSL_PllcResetDef     */    CSL_PLLC_CMD_DEFINE_RESET,    /** \brief By setting the ALN bits, the selected SYSCLKx (specified by     *         input bitmask) will always be phase aligned to other clocks     *         also selected in this register     *  \param CSL_BitMask32     *  \return CSL_SOK     *  \sa CSL_PLLC_ALIGNCTL_DEFINE     */    CSL_PLLC_CMD_SET_PHASEALIGN,    /** \brief Set PLL multiplier value     *  \param Uint32     *  \return CSL_SOK