?? cslr_gpio.h
字號:
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** \file cslr_gpio.h
*
* \brief This file contains the Register Desciptions for GPIO
*
*********************************************************************/
#ifndef _CSLR_GPIO_H_
#define _CSLR_GPIO_H_
/* ============================================================================
* Revision History
* ===============
* 04-Sep-2004 Nsr renamed from CSLR_GPIO_001.h
*
* ============================================================================
*/
#define CSL_GPIO_NUM_PINS (69)
#define CSL_MGPIO_NUM_PINS (130)
#define CSL_GPIO_NUM_BANKS (CSL_GPIO_NUM_PINS + 15)/16
#define CSL_MGPIO_NUM_BANKS (CSL_MGPIO_NUM_PINS + 15)/16
typedef enum {
CSL_GPIO_PIN0,
CSL_GPIO_PIN1,
CSL_GPIO_PIN2,
CSL_GPIO_PIN3,
CSL_GPIO_PIN4,
CSL_GPIO_PIN5,
CSL_GPIO_PIN6,
CSL_GPIO_PIN7,
CSL_GPIO_PIN8,
CSL_GPIO_PIN9,
CSL_GPIO_PIN10,
CSL_GPIO_PIN11,
CSL_GPIO_PIN12,
CSL_GPIO_PIN13,
CSL_GPIO_PIN14,
CSL_GPIO_PIN15,
CSL_GPIO_PIN16,
CSL_GPIO_PIN17,
CSL_GPIO_PIN18,
CSL_GPIO_PIN19,
CSL_GPIO_PIN20,
CSL_GPIO_PIN21,
CSL_GPIO_PIN22,
CSL_GPIO_PIN23,
CSL_GPIO_PIN24,
CSL_GPIO_PIN25,
CSL_GPIO_PIN26,
CSL_GPIO_PIN27,
CSL_GPIO_PIN28,
CSL_GPIO_PIN29,
CSL_GPIO_PIN30,
CSL_GPIO_PIN31,
CSL_GPIO_PIN32,
CSL_GPIO_PIN33,
CSL_GPIO_PIN34,
CSL_GPIO_PIN35,
CSL_GPIO_PIN36,
CSL_GPIO_PIN37,
CSL_GPIO_PIN38,
CSL_GPIO_PIN39,
CSL_GPIO_PIN40,
CSL_GPIO_PIN41,
CSL_GPIO_PIN42,
CSL_GPIO_PIN43,
CSL_GPIO_PIN44,
CSL_GPIO_PIN45,
CSL_GPIO_PIN46,
CSL_GPIO_PIN47,
CSL_GPIO_PIN48,
CSL_GPIO_PIN49,
CSL_GPIO_PIN50,
CSL_GPIO_PIN51,
CSL_GPIO_PIN52,
CSL_GPIO_PIN53,
CSL_GPIO_PIN54,
CSL_GPIO_PIN55,
CSL_GPIO_PIN56,
CSL_GPIO_PIN57,
CSL_GPIO_PIN58,
CSL_GPIO_PIN59,
CSL_GPIO_PIN60,
CSL_GPIO_PIN61,
CSL_GPIO_PIN62,
CSL_GPIO_PIN63,
CSL_GPIO_PIN64,
CSL_GPIO_PIN65,
CSL_GPIO_PIN66,
CSL_GPIO_PIN67,
CSL_GPIO_PIN68,
CSL_GPIO_PIN69,
CSL_GPIO_PIN70,
CSL_GPIO_PIN71,
CSL_GPIO_PIN72,
CSL_GPIO_PIN73,
CSL_GPIO_PIN74,
CSL_GPIO_PIN75,
CSL_GPIO_PIN76,
CSL_GPIO_PIN77,
CSL_GPIO_PIN78,
CSL_GPIO_PIN79,
CSL_GPIO_PIN80,
CSL_GPIO_PIN81,
CSL_GPIO_PIN82,
CSL_GPIO_PIN83,
CSL_GPIO_PIN84,
CSL_GPIO_PIN85,
CSL_GPIO_PIN86,
CSL_GPIO_PIN87,
CSL_GPIO_PIN88,
CSL_GPIO_PIN89,
CSL_GPIO_PIN90,
CSL_GPIO_PIN91,
CSL_GPIO_PIN92,
CSL_GPIO_PIN93,
CSL_GPIO_PIN94,
CSL_GPIO_PIN95,
CSL_GPIO_PIN96,
CSL_GPIO_PIN97,
CSL_GPIO_PIN98,
CSL_GPIO_PIN99,
CSL_GPIO_PIN100,
CSL_GPIO_PIN101,
CSL_GPIO_PIN102,
CSL_GPIO_PIN103,
CSL_GPIO_PIN104,
CSL_GPIO_PIN105,
CSL_GPIO_PIN106,
CSL_GPIO_PIN107,
CSL_GPIO_PIN108,
CSL_GPIO_PIN109,
CSL_GPIO_PIN110,
CSL_GPIO_PIN111,
CSL_GPIO_PIN112,
CSL_GPIO_PIN113,
CSL_GPIO_PIN114,
CSL_GPIO_PIN115,
CSL_GPIO_PIN116,
CSL_GPIO_PIN117,
CSL_GPIO_PIN118,
CSL_GPIO_PIN119,
CSL_GPIO_PIN120,
CSL_GPIO_PIN121,
CSL_GPIO_PIN122,
CSL_GPIO_PIN123,
CSL_GPIO_PIN124,
CSL_GPIO_PIN125,
CSL_GPIO_PIN126,
CSL_GPIO_PIN127,
CSL_GPIO_PIN128,
CSL_GPIO_PIN129
} CSL_GpioPinNum;
typedef enum {
CSL_GPIO_BANK0 = 1,
CSL_GPIO_BANK1 = 2,
CSL_GPIO_BANK2 = 3,
CSL_GPIO_BANK3 = 4,
CSL_GPIO_BANK4 = 5,
CSL_GPIO_BANK5 = 6,
CSL_GPIO_BANK6 = 7,
CSL_GPIO_BANK7 = 8,
CSL_GPIO_BANK8 = 9
} CSL_GpioBankNum;
/**************************************************************************\
* Register Overlay Structure for BANK
\**************************************************************************/
typedef struct {
volatile Uint32 DIR;
volatile Uint32 OUT_DATA;
volatile Uint32 SET_DATA;
volatile Uint32 CLR_DATA;
volatile Uint32 IN_DATA;
volatile Uint32 SET_RIS_TRIG;
volatile Uint32 CLR_RIS_TRIG;
volatile Uint32 SET_FAL_TRIG;
volatile Uint32 CLR_FAL_TRIG;
volatile Uint32 INTSTAT;
} CSL_GpioBankRegs;
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 PID;
volatile Uint32 PCR;
volatile Uint32 BINTEN;
volatile Uint8 RSVD0[4];
CSL_GpioBankRegs BANK[5];
} CSL_GpioRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_GpioRegs *CSL_GpioRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* PID */
#define CSL_GPIO_PID_TID_MASK (0x00FF0000u)
#define CSL_GPIO_PID_TID_SHIFT (0x00000010u)
#define CSL_GPIO_PID_TID_RESETVAL (0x00000000u)
#define CSL_GPIO_PID_CID_MASK (0x0000FF00u)
#define CSL_GPIO_PID_CID_SHIFT (0x00000008u)
#define CSL_GPIO_PID_CID_RESETVAL (0x00000000u)
#define CSL_GPIO_PID_REV_MASK (0x000000FFu)
#define CSL_GPIO_PID_REV_SHIFT (0x00000000u)
#define CSL_GPIO_PID_REV_RESETVAL (0x00000000u)
#define CSL_GPIO_PID_RESETVAL (0x00000000u)
/* PCR */
#define CSL_GPIO_PCR_SOFT_MASK (0x00000002u)
#define CSL_GPIO_PCR_SOFT_SHIFT (0x00000001u)
#define CSL_GPIO_PCR_SOFT_RESETVAL (0x00000000u)
#define CSL_GPIO_PCR_FREE_MASK (0x00000001u)
#define CSL_GPIO_PCR_FREE_SHIFT (0x00000000u)
#define CSL_GPIO_PCR_FREE_RESETVAL (0x00000001u)
#define CSL_GPIO_PCR_RESETVAL (0x00000001u)
/* BINTEN */
#define CSL_GPIO_BINTEN_RESERVED_MASK (0xFFFFFE00u)
#define CSL_GPIO_BINTEN_RESERVED_SHIFT (0x00000009u)
#define CSL_GPIO_BINTEN_RESERVED_RESETVAL (0x00000000u)
#define CSL_GPIO_BINTEN_EN8_MASK (0x00000100u)
#define CSL_GPIO_BINTEN_EN8_SHIFT (0x00000008u)
#define CSL_GPIO_BINTEN_EN8_RESETVAL (0x00000000u)
#define CSL_GPIO_BINTEN_EN7_MASK (0x00000080u)
#define CSL_GPIO_BINTEN_EN7_SHIFT (0x00000007u)
#define CSL_GPIO_BINTEN_EN7_RESETVAL (0x00000000u)
#define CSL_GPIO_BINTEN_EN6_MASK (0x00000040u)
#define CSL_GPIO_BINTEN_EN6_SHIFT (0x00000006u)
#define CSL_GPIO_BINTEN_EN6_RESETVAL (0x00000000u)
#define CSL_GPIO_BINTEN_EN5_MASK (0x00000020u)
#define CSL_GPIO_BINTEN_EN5_SHIFT (0x00000005u)
#define CSL_GPIO_BINTEN_EN5_RESETVAL (0x00000000u)
#define CSL_GPIO_BINTEN_EN4_MASK (0x00000010u)
#define CSL_GPIO_BINTEN_EN4_SHIFT (0x00000004u)
#define CSL_GPIO_BINTEN_EN4_RESETVAL (0x00000000u)
#define CSL_GPIO_BINTEN_EN3_MASK (0x00000008u)
#define CSL_GPIO_BINTEN_EN3_SHIFT (0x00000003u)
#define CSL_GPIO_BINTEN_EN3_RESETVAL (0x00000000u)
#define CSL_GPIO_BINTEN_EN2_MASK (0x00000004u)
#define CSL_GPIO_BINTEN_EN2_SHIFT (0x00000002u)
#define CSL_GPIO_BINTEN_EN2_RESETVAL (0x00000000u)
#define CSL_GPIO_BINTEN_EN1_MASK (0x00000002u)
#define CSL_GPIO_BINTEN_EN1_SHIFT (0x00000001u)
#define CSL_GPIO_BINTEN_EN1_RESETVAL (0x00000000u)
#define CSL_GPIO_BINTEN_EN0_MASK (0x00000001u)
#define CSL_GPIO_BINTEN_EN0_SHIFT (0x00000000u)
#define CSL_GPIO_BINTEN_EN0_RESETVAL (0x00000000u)
/*----EN Tokens----*/
#define CSL_GPIO_BINTEN_EN_DISABLE (0x00000000u)
#define CSL_GPIO_BINTEN_EN_ENABLE (0x00000001u)
#define CSL_GPIO_BINTEN_RESETVAL (0x00000000u)
/* DIR */
#define CSL_GPIO_DIR_DIR31_MASK (0x80000000u)
#define CSL_GPIO_DIR_DIR31_SHIFT (0x0000001Fu)
#define CSL_GPIO_DIR_DIR31_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR30_MASK (0x40000000u)
#define CSL_GPIO_DIR_DIR30_SHIFT (0x0000001Eu)
#define CSL_GPIO_DIR_DIR30_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR29_MASK (0x20000000u)
#define CSL_GPIO_DIR_DIR29_SHIFT (0x0000001Du)
#define CSL_GPIO_DIR_DIR29_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR28_MASK (0x10000000u)
#define CSL_GPIO_DIR_DIR28_SHIFT (0x0000001Cu)
#define CSL_GPIO_DIR_DIR28_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR27_MASK (0x08000000u)
#define CSL_GPIO_DIR_DIR27_SHIFT (0x0000001Bu)
#define CSL_GPIO_DIR_DIR27_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR26_MASK (0x04000000u)
#define CSL_GPIO_DIR_DIR26_SHIFT (0x0000001Au)
#define CSL_GPIO_DIR_DIR26_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR25_MASK (0x02000000u)
#define CSL_GPIO_DIR_DIR25_SHIFT (0x00000019u)
#define CSL_GPIO_DIR_DIR25_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR24_MASK (0x01000000u)
#define CSL_GPIO_DIR_DIR24_SHIFT (0x00000018u)
#define CSL_GPIO_DIR_DIR24_RESETVAL (0x00000001u)
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -