?? csl_pllcaux.h
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* @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc CKEN register @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n The miscellaneous output clocks are disabled. * * @b Modifies * @n pllc CKEN register. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_BitMask32 loadVal; ... CSL_pllcClockDisable (hPllc, loadVal); @endverbatim * ============================================================================= */CSL_IDEF_INLINEvoid CSL_pllcClockDisable ( CSL_PllcHandle hPllc, CSL_BitMask32 loadVal){ hPllc->regs->CKEN &= ~(loadVal);}/** ============================================================================ * @n@b CSL_pllcDefineReset * * @b Description * Sets the operation caused by external warm reset pin. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc RSTDEF register @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n pllc operation caused by reset is defined according to set value. * * @b Modifies * @n pllc RSTDEF register. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_PllcResetDef loadVal; ... CSL_pllcDefineReset (hPllc, loadVal); @endverbatim * ============================================================================= */CSL_IDEF_INLINEvoid CSL_pllcDefineReset ( CSL_PllcHandle hPllc, CSL_PllcResetDef loadVal){ CSL_FINS (hPllc->regs->RSTDEF, PLLC_RSTDEF_XWFUNC, loadVal);}/** ============================================================================ * @n@b CSL_pllcSetPhaseAlignCtrl * * @b Description * Controls Phase Alignment of System clocks. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc ALNCTL register @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n Phase alignment of system clocks is controlled. * * @b Modifies * @n pllc ALNCTL register. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_BitMask32 loadVal; ... CSL_pllcSetPhaseAlignCtrl (hPllc, loadVal); @endverbatim * ============================================================================= */CSL_IDEF_INLINEvoid CSL_pllcSetPhaseAlignCtrl ( CSL_PllcHandle hPllc, CSL_BitMask32 loadVal){ while (CSL_FEXT (hPllc->regs->PLLSTAT, PLLC_PLLSTAT_GOSTAT)) { /* GO operation is in progress */ } hPllc->regs->ALNCTL = loadVal;}/** ============================================================================ * @n@b CSL_pllcMultiplierCtrl * * @b Description * Controls the pllc Multiplier. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc PLLM register @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n pllc multiplier is controlled accordingly. * * @b Modifies * @n pllc PLLM register. * * @b Example * @verbatim CSL_PllcHandle hPllc; Uint32 loadVal; ... CSL_pllcMultiplierCtrl (hPllc, loadVal); @endverbatim * ============================================================================= */CSL_IDEF_INLINEvoid CSL_pllcMultiplierCtrl ( CSL_PllcHandle hPllc, Uint32 loadVal){ CSL_FINS (hPllc->regs->PLLM, PLLC_PLLM_PLLM, loadVal);}/** ============================================================================ * @n@b CSL_pllcSetOscDivRatio * * @b Description * Set the pllc Oscillator Divider Ratio. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc OSCDIV1 register @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n The pllc Oscillator Divider Ratio is set. * * @b Modifies * @n pllc OSCDIV1 register. * * @b Example * @verbatim CSL_PllcHandle hPllc; Uint32 loadVal; ... CSL_pllcSetOscDivRatio (hPllc, loadVal); @endverbatim * ============================================================================= */CSL_IDEF_INLINEvoid CSL_pllcSetOscDivRatio ( CSL_PllcHandle hPllc, Uint32 loadVal){ CSL_FINS (hPllc->regs->OSCDIV1, PLLC_OSCDIV1_RATIO, loadVal);}/** ============================================================================ * @n@b CSL_pllcSetPLLDivRatio * * @b Description * Sets the pllc Dividers ratios. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc divider registers status Status variable @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n pllc dividers ratios are set. * * @b Modifies * @n pllc divider registers. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_PllcDivRatio loadVal; CSL_Status status; ... CSL_pllcSetPLLDivRatio (hPllc, loadVal, &status); @endverbatim * ============================================================================= */CSL_IDEF_INLINEvoid CSL_pllcSetPLLDivRatio ( CSL_PllcHandle hPllc, CSL_PllcDivRatio loadVal, CSL_Status *status){ switch (loadVal.divNum) { case CSL_PLLC_DIVSEL_PLLDIV1: CSL_FINS (hPllc->regs->PLLDIV1, PLLC_PLLDIV1_RATIO, (Uint32)loadVal.divRatio); break; case CSL_PLLC_DIVSEL_PLLDIV2: CSL_FINS (hPllc->regs->PLLDIV2, PLLC_PLLDIV2_RATIO, (Uint32)loadVal.divRatio); break; case CSL_PLLC_DIVSEL_PLLDIV3: CSL_FINS (hPllc->regs->PLLDIV3, PLLC_PLLDIV3_RATIO, (Uint32)loadVal.divRatio); break; case CSL_PLLC_DIVSEL_PLLDIV4: CSL_FINS (hPllc->regs->PLLDIV4, PLLC_PLLDIV4_RATIO, (Uint32)loadVal.divRatio); break; case CSL_PLLC_DIVSEL_PLLDIV5: CSL_FINS (hPllc->regs->PLLDIV5, PLLC_PLLDIV5_RATIO, (Uint32)loadVal.divRatio); break; case CSL_PLLC_DIVSEL_PLLDIV6: CSL_FINS (hPllc->regs->PLLDIV6, PLLC_PLLDIV6_RATIO, (Uint32)loadVal.divRatio); break; case CSL_PLLC_DIVSEL_PLLDIV7: CSL_FINS (hPllc->regs->PLLDIV7, PLLC_PLLDIV7_RATIO, (Uint32)loadVal.divRatio); break; case CSL_PLLC_DIVSEL_PLLDIV8: CSL_FINS (hPllc->regs->PLLDIV8, PLLC_PLLDIV8_RATIO, (Uint32)loadVal.divRatio); break; default: *status = CSL_ESYS_INVPARAMS; break; }}/** ============================================================================ * @n@b CSL_pllcOscDivCtrl * * @b Description * Controls the pllc Oscillator Divider. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc OSCDIV1 register @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n pllc oscillator divider is controlled according to value set. * * @b Modifies * @n pllc OSCDIV1 register. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_PllcOscDivCtrl loadVal; ... CSL_pllcOscDivCtrl (hPllc, loadVal); @endverbatim * ============================================================================= */CSL_IDEF_INLINEvoid CSL_pllcOscDivCtrl ( CSL_PllcHandle hPllc, CSL_PllcOscDivCtrl loadVal){ CSL_FINS (hPllc->regs->OSCDIV1, PLLC_OSCDIV1_OD1EN, loadVal);}/** ============================================================================ * @n@b CSL_pllcPLLDivCtrl * * @b Description * Controls the pllc dividers. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc dividers register. status Status variable @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n pllc dividers are controlled. * * @b Modifies * @n pllc dividers register. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_PllcDivideControl loadVal; CSL_Status status; ... CSL_pllcPLLDivCtrl (hPllc, loadVal, &status); @endverbatim * ============================================================================= */CSL_IDEF_INLINEvoid CSL_pllcPLLDivCtrl ( CSL_PllcHandle hPllc, CSL_PllcDivideControl loadVal, CSL_Status *status){ switch (loadVal.divNum) { case CSL_PLLC_DIVSEL_PLLDIV1: CSL_FINS (hPllc->regs->PLLDIV1, PLLC_PLLDIV1_D1EN, (CSL_PllcDivCtrl)loadVal.divCtrl); break; case CSL_PLLC_DIVSEL_PLLDIV2: CSL_FINS (hPllc->regs->PLLDIV2, PLLC_PLLDIV2_D2EN, (CSL_PllcDivCtrl)loadVal.divCtrl); break; case CSL_PLLC_DIVSEL_PLLDIV3: CSL_FINS (hPllc->regs->PLLDIV3, PLLC_PLLDIV3_D3EN, (CSL_PllcDivCtrl)loadVal.divCtrl); break; case CSL_PLLC_DIVSEL_PLLDIV4: CSL_FINS (hPllc->regs->PLLDIV4, PLLC_PLLDIV4_D4EN, (CSL_PllcDivCtrl)loadVal.divCtrl); break; case CSL_PLLC_DIVSEL_PLLDIV5: CSL_FINS (hPllc->regs->PLLDIV5, PLLC_PLLDIV5_D5EN, (CSL_PllcDivCtrl)loadVal.divCtrl); break; case CSL_PLLC_DIVSEL_PLLDIV6: CSL_FINS (hPllc->regs->PLLDIV6, PLLC_PLLDIV6_D6EN, (CSL_PllcDivCtrl)loadVal.divCtrl); break; case CSL_PLLC_DIVSEL_PLLDIV7: CSL_FINS (hPllc->regs->PLLDIV7, PLLC_PLLDIV7_D7EN, (CSL_PllcDivCtrl)loadVal.divCtrl); break; case CSL_PLLC_DIVSEL_PLLDIV8: CSL_FINS (hPllc->regs->PLLDIV8, PLLC_PLLDIV8_D8EN, (CSL_PllcDivCtrl)loadVal.divCtrl); break; default: *status = CSL_ESYS_INVPARAMS; break; }}/** ============================================================================ * @n@b CSL_pllcCmdWakeup * * @b Description * Controls the pllc wakeup operation. * * @b Arguments * @verbatim hPllc Handle to the PLLC instance loadVal Value to be loaded to pllc WAKEUP register @endverbatim * * <b> Return Value </b> * @n None * * <b> Pre Condition </b> * @n None * * <b> Post Condition </b> * @n pllc wakeup operation is controlled. * * @b Modifies * @n pllc WAKEUP register. * * @b Example * @verbatim CSL_PllcHandle hPllc; CSL_BitMask16 loadVal; ... CSL_pllcCmdWakeup (hPllc, loadVal); @endverbatim * ============================================================================= */CSL_IDEF_INLINEvoid CSL_pllcCmdWakeup ( CSL_PllcHandle hPllc, CSL_BitMask16 loadVal){ hPllc->regs->WAKEUP = loadVal;}#ifdef __cplusplus}#endif#endif /* _CSL_PLLCAUX_H_ */?? 快捷鍵說明
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