?? cslr_nand.h

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/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005                 
 *                                                                              
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.             
 *   ===========================================================================
 */

#ifndef _CSLR_NAND_H_
#define _CSLR_NAND_H_

/** \file cslr_nand.h
 * 
 * \brief This file contains the Register Desciptions for NAND
 * 
 *********************************************************************/

/* =============================================================================
 *  Revision History
 *  ===============
 *  03-sep-2004 Nsr renamed from CSLR_NAND_001.h
 *
 * =============================================================================
 */

#include <cslr.h>
#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 NRCSR;
    volatile Uint32 AWCCR;
    volatile Uint8 RSVD0[8];
    volatile Uint32 AB1CR;
    volatile Uint32 AB2CR;
    volatile Uint32 AB3CR;
    volatile Uint32 AB4CR;
    volatile Uint8 RSVD1[32];
    volatile Uint32 NIRR;
    volatile Uint32 NIMR;
    volatile Uint32 NIMSR;
    volatile Uint32 NIMCR;
    volatile Uint8 RSVD2[16];
    volatile Uint32 NANDFCR;
    volatile Uint32 NANDFSR;
    volatile Uint8 RSVD3[8];
    volatile Uint32 NANDF1ECC;
    volatile Uint32 NANDF2ECC;
    volatile Uint32 NANDF3ECC;
    volatile Uint32 NANDF4ECC;
    volatile Uint8 RSVD4[4];
    volatile Uint32 IODFTECR;
    volatile Uint32 IODFTGCR;
    volatile Uint8 RSVD5[4];
    volatile Uint32 IODFTMRLR;
    volatile Uint32 IODFTMRMR;
    volatile Uint32 IODFTMRMSBR;
    volatile Uint8 RSVD6[20];
    volatile Uint32 MODRNR;
    volatile Uint8 RSVD7[76];
    volatile Uint32 CE0DATA;
    volatile Uint32 CE0ALE;
    volatile Uint32 CE0CLE;
    volatile Uint8 RSVD8[4];
    volatile Uint32 CE1DATA;
    volatile Uint32 CE1ALE;
    volatile Uint32 CE1CLE;
    volatile Uint8 RSVD9[4];
    volatile Uint32 CE2DATA;
    volatile Uint32 CE2ALE;
    volatile Uint32 CE2CLE;
    volatile Uint8 RSVD10[4];
    volatile Uint32 CE3DATA;
    volatile Uint32 CE3ALE;
    volatile Uint32 CE3CLE;
} CSL_NandRegs;

/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_NandRegs             *CSL_NandRegsOvly;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* NRCSR */

#define CSL_NAND_NRCSR_BE_MASK           (0x80000000u)
#define CSL_NAND_NRCSR_BE_SHIFT          (0x0000001Fu)
#define CSL_NAND_NRCSR_BE_RESETVAL       (0x00000001u)

#define CSL_NAND_NRCSR_FR_MASK           (0x40000000u)
#define CSL_NAND_NRCSR_FR_SHIFT          (0x0000001Eu)
#define CSL_NAND_NRCSR_FR_RESETVAL       (0x00000001u)

#define CSL_NAND_NRCSR_MID_MASK          (0x3FFF0000u)
#define CSL_NAND_NRCSR_MID_SHIFT         (0x00000010u)
#define CSL_NAND_NRCSR_MID_RESETVAL      (0x00000000u)

#define CSL_NAND_NRCSR_MAJREV_MASK       (0x0000FF00u)
#define CSL_NAND_NRCSR_MAJREV_SHIFT      (0x00000008u)
#define CSL_NAND_NRCSR_MAJREV_RESETVAL   (0x00000002u)

#define CSL_NAND_NRCSR_MINREV_MASK       (0x000000FFu)
#define CSL_NAND_NRCSR_MINREV_SHIFT      (0x00000000u)
#define CSL_NAND_NRCSR_MINREV_RESETVAL   (0x00000001u)

#define CSL_NAND_NRCSR_RESETVAL          (0xC0000201u)

/* AWCCR */

#define CSL_NAND_AWCCR_WP3_MASK          (0x80000000u)
#define CSL_NAND_AWCCR_WP3_SHIFT         (0x0000001Fu)
#define CSL_NAND_AWCCR_WP3_RESETVAL      (0x00000001u)

#define CSL_NAND_AWCCR_WP2_MASK          (0x40000000u)
#define CSL_NAND_AWCCR_WP2_SHIFT         (0x0000001Eu)
#define CSL_NAND_AWCCR_WP2_RESETVAL      (0x00000001u)

#define CSL_NAND_AWCCR_WP1_MASK          (0x20000000u)
#define CSL_NAND_AWCCR_WP1_SHIFT         (0x0000001Du)
#define CSL_NAND_AWCCR_WP1_RESETVAL      (0x00000001u)

#define CSL_NAND_AWCCR_WP0_MASK          (0x10000000u)
#define CSL_NAND_AWCCR_WP0_SHIFT         (0x0000001Cu)
#define CSL_NAND_AWCCR_WP0_RESETVAL      (0x00000001u)

#define CSL_NAND_AWCCR_CS3WAIT_MASK      (0x00C00000u)
#define CSL_NAND_AWCCR_CS3WAIT_SHIFT     (0x00000016u)
#define CSL_NAND_AWCCR_CS3WAIT_RESETVAL  (0x00000000u)

#define CSL_NAND_AWCCR_CS2WAIT_MASK      (0x00300000u)
#define CSL_NAND_AWCCR_CS2WAIT_SHIFT     (0x00000014u)
#define CSL_NAND_AWCCR_CS2WAIT_RESETVAL  (0x00000000u)

#define CSL_NAND_AWCCR_CS1WAIT_MASK      (0x000C0000u)
#define CSL_NAND_AWCCR_CS1WAIT_SHIFT     (0x00000012u)
#define CSL_NAND_AWCCR_CS1WAIT_RESETVAL  (0x00000000u)

#define CSL_NAND_AWCCR_CS0WAIT_MASK      (0x00030000u)
#define CSL_NAND_AWCCR_CS0WAIT_SHIFT     (0x00000010u)
#define CSL_NAND_AWCCR_CS0WAIT_RESETVAL  (0x00000000u)

#define CSL_NAND_AWCCR_MEWC_MASK         (0x000000FFu)
#define CSL_NAND_AWCCR_MEWC_SHIFT        (0x00000000u)
#define CSL_NAND_AWCCR_MEWC_RESETVAL     (0x00000080u)

#define CSL_NAND_AWCCR_RESETVAL          (0xF0000080u)

/* AB1CR */

#define CSL_NAND_AB1CR_SS_MASK           (0x80000000u)
#define CSL_NAND_AB1CR_SS_SHIFT          (0x0000001Fu)
#define CSL_NAND_AB1CR_SS_RESETVAL       (0x00000000u)

#define CSL_NAND_AB1CR_EW_MASK           (0x40000000u)
#define CSL_NAND_AB1CR_EW_SHIFT          (0x0000001Eu)
#define CSL_NAND_AB1CR_EW_RESETVAL       (0x00000000u)

#define CSL_NAND_AB1CR_W_SETUP_MASK      (0x3C000000u)
#define CSL_NAND_AB1CR_W_SETUP_SHIFT     (0x0000001Au)
#define CSL_NAND_AB1CR_W_SETUP_RESETVAL  (0x0000000Fu)

#define CSL_NAND_AB1CR_W_STROBE_MASK     (0x03F00000u)
#define CSL_NAND_AB1CR_W_STROBE_SHIFT    (0x00000014u)
#define CSL_NAND_AB1CR_W_STROBE_RESETVAL (0x0000003Fu)

#define CSL_NAND_AB1CR_W_HOLD_MASK       (0x000E0000u)
#define CSL_NAND_AB1CR_W_HOLD_SHIFT      (0x00000011u)
#define CSL_NAND_AB1CR_W_HOLD_RESETVAL   (0x00000007u)

#define CSL_NAND_AB1CR_R_SETUP_MASK      (0x0001E000u)
#define CSL_NAND_AB1CR_R_SETUP_SHIFT     (0x0000000Du)
#define CSL_NAND_AB1CR_R_SETUP_RESETVAL  (0x0000000Fu)

#define CSL_NAND_AB1CR_R_STROBE_MASK     (0x00001F80u)
#define CSL_NAND_AB1CR_R_STROBE_SHIFT    (0x00000007u)
#define CSL_NAND_AB1CR_R_STROBE_RESETVAL (0x0000003Fu)

#define CSL_NAND_AB1CR_R_HOLD_MASK       (0x00000070u)
#define CSL_NAND_AB1CR_R_HOLD_SHIFT      (0x00000004u)
#define CSL_NAND_AB1CR_R_HOLD_RESETVAL   (0x00000007u)

#define CSL_NAND_AB1CR_TA_MASK           (0x0000000Cu)
#define CSL_NAND_AB1CR_TA_SHIFT          (0x00000002u)
#define CSL_NAND_AB1CR_TA_RESETVAL       (0x00000003u)

#define CSL_NAND_AB1CR_ASIZE_MASK        (0x00000003u)
#define CSL_NAND_AB1CR_ASIZE_SHIFT       (0x00000000u)
#define CSL_NAND_AB1CR_ASIZE_RESETVAL    (0x00000001u)

/*----ASIZE Tokens----*/
#define CSL_NAND_AB1CR_ASIZE_DATA8       (0x00000000u)
#define CSL_NAND_AB1CR_ASIZE_DATA16      (0x00000001u)

#define CSL_NAND_AB1CR_RESETVAL          (0x3FFFFFFDu)

/* AB2CR */

#define CSL_NAND_AB2CR_SS_MASK           (0x80000000u)
#define CSL_NAND_AB2CR_SS_SHIFT          (0x0000001Fu)
#define CSL_NAND_AB2CR_SS_RESETVAL       (0x00000000u)

#define CSL_NAND_AB2CR_EW_MASK           (0x40000000u)
#define CSL_NAND_AB2CR_EW_SHIFT          (0x0000001Eu)
#define CSL_NAND_AB2CR_EW_RESETVAL       (0x00000000u)

#define CSL_NAND_AB2CR_W_SETUP_MASK      (0x3C000000u)
#define CSL_NAND_AB2CR_W_SETUP_SHIFT     (0x0000001Au)
#define CSL_NAND_AB2CR_W_SETUP_RESETVAL  (0x0000000Fu)

#define CSL_NAND_AB2CR_W_STROBE_MASK     (0x03F00000u)
#define CSL_NAND_AB2CR_W_STROBE_SHIFT    (0x00000014u)
#define CSL_NAND_AB2CR_W_STROBE_RESETVAL (0x0000003Fu)

#define CSL_NAND_AB2CR_W_HOLD_MASK       (0x000E0000u)
#define CSL_NAND_AB2CR_W_HOLD_SHIFT      (0x00000011u)
#define CSL_NAND_AB2CR_W_HOLD_RESETVAL   (0x00000007u)

#define CSL_NAND_AB2CR_R_SETUP_MASK      (0x0001E000u)
#define CSL_NAND_AB2CR_R_SETUP_SHIFT     (0x0000000Du)
#define CSL_NAND_AB2CR_R_SETUP_RESETVAL  (0x0000000Fu)

#define CSL_NAND_AB2CR_R_STROBE_MASK     (0x00001F80u)
#define CSL_NAND_AB2CR_R_STROBE_SHIFT    (0x00000007u)
#define CSL_NAND_AB2CR_R_STROBE_RESETVAL (0x0000003Fu)

#define CSL_NAND_AB2CR_R_HOLD_MASK       (0x00000070u)
#define CSL_NAND_AB2CR_R_HOLD_SHIFT      (0x00000004u)
#define CSL_NAND_AB2CR_R_HOLD_RESETVAL   (0x00000007u)

#define CSL_NAND_AB2CR_TA_MASK           (0x0000000Cu)
#define CSL_NAND_AB2CR_TA_SHIFT          (0x00000002u)
#define CSL_NAND_AB2CR_TA_RESETVAL       (0x00000003u)

#define CSL_NAND_AB2CR_ASIZE_MASK        (0x00000003u)
#define CSL_NAND_AB2CR_ASIZE_SHIFT       (0x00000000u)
#define CSL_NAND_AB2CR_ASIZE_RESETVAL    (0x00000001u)

/*----ASIZE Tokens----*/
#define CSL_NAND_AB2CR_ASIZE_DATA8       (0x00000000u)
#define CSL_NAND_AB2CR_ASIZE_DATA16      (0x00000001u)

#define CSL_NAND_AB2CR_RESETVAL          (0x3FFFFFFDu)

/* AB3CR */

#define CSL_NAND_AB3CR_SS_MASK           (0x80000000u)
#define CSL_NAND_AB3CR_SS_SHIFT          (0x0000001Fu)
#define CSL_NAND_AB3CR_SS_RESETVAL       (0x00000000u)

#define CSL_NAND_AB3CR_EW_MASK           (0x40000000u)
#define CSL_NAND_AB3CR_EW_SHIFT          (0x0000001Eu)
#define CSL_NAND_AB3CR_EW_RESETVAL       (0x00000000u)

#define CSL_NAND_AB3CR_W_SETUP_MASK      (0x3C000000u)
#define CSL_NAND_AB3CR_W_SETUP_SHIFT     (0x0000001Au)
#define CSL_NAND_AB3CR_W_SETUP_RESETVAL  (0x0000000Fu)

#define CSL_NAND_AB3CR_W_STROBE_MASK     (0x03F00000u)
#define CSL_NAND_AB3CR_W_STROBE_SHIFT    (0x00000014u)
#define CSL_NAND_AB3CR_W_STROBE_RESETVAL (0x0000003Fu)

#define CSL_NAND_AB3CR_W_HOLD_MASK       (0x000E0000u)
#define CSL_NAND_AB3CR_W_HOLD_SHIFT      (0x00000011u)
#define CSL_NAND_AB3CR_W_HOLD_RESETVAL   (0x00000007u)

#define CSL_NAND_AB3CR_R_SETUP_MASK      (0x0001E000u)
#define CSL_NAND_AB3CR_R_SETUP_SHIFT     (0x0000000Du)
#define CSL_NAND_AB3CR_R_SETUP_RESETVAL  (0x0000000Fu)

#define CSL_NAND_AB3CR_R_STROBE_MASK     (0x00001F80u)
#define CSL_NAND_AB3CR_R_STROBE_SHIFT    (0x00000007u)
#define CSL_NAND_AB3CR_R_STROBE_RESETVAL (0x0000003Fu)

#define CSL_NAND_AB3CR_R_HOLD_MASK       (0x00000070u)
#define CSL_NAND_AB3CR_R_HOLD_SHIFT      (0x00000004u)
#define CSL_NAND_AB3CR_R_HOLD_RESETVAL   (0x00000007u)

#define CSL_NAND_AB3CR_TA_MASK           (0x0000000Cu)
#define CSL_NAND_AB3CR_TA_SHIFT          (0x00000002u)
#define CSL_NAND_AB3CR_TA_RESETVAL       (0x00000003u)

#define CSL_NAND_AB3CR_ASIZE_MASK        (0x00000003u)
#define CSL_NAND_AB3CR_ASIZE_SHIFT       (0x00000000u)
#define CSL_NAND_AB3CR_ASIZE_RESETVAL    (0x00000001u)

/*----ASIZE Tokens----*/
#define CSL_NAND_AB3CR_ASIZE_DATA8       (0x00000000u)
#define CSL_NAND_AB3CR_ASIZE_DATA16      (0x00000001u)

#define CSL_NAND_AB3CR_RESETVAL          (0x3FFFFFFDu)

/* AB4CR */

#define CSL_NAND_AB4CR_SS_MASK           (0x80000000u)
#define CSL_NAND_AB4CR_SS_SHIFT          (0x0000001Fu)
#define CSL_NAND_AB4CR_SS_RESETVAL       (0x00000000u)

#define CSL_NAND_AB4CR_EW_MASK           (0x40000000u)
#define CSL_NAND_AB4CR_EW_SHIFT          (0x0000001Eu)
#define CSL_NAND_AB4CR_EW_RESETVAL       (0x00000000u)

#define CSL_NAND_AB4CR_W_SETUP_MASK      (0x3C000000u)
#define CSL_NAND_AB4CR_W_SETUP_SHIFT     (0x0000001Au)
#define CSL_NAND_AB4CR_W_SETUP_RESETVAL  (0x0000000Fu)

#define CSL_NAND_AB4CR_W_STROBE_MASK     (0x03F00000u)
#define CSL_NAND_AB4CR_W_STROBE_SHIFT    (0x00000014u)
#define CSL_NAND_AB4CR_W_STROBE_RESETVAL (0x0000003Fu)

#define CSL_NAND_AB4CR_W_HOLD_MASK       (0x000E0000u)
#define CSL_NAND_AB4CR_W_HOLD_SHIFT      (0x00000011u)
#define CSL_NAND_AB4CR_W_HOLD_RESETVAL   (0x00000007u)

#define CSL_NAND_AB4CR_R_SETUP_MASK      (0x0001E000u)
#define CSL_NAND_AB4CR_R_SETUP_SHIFT     (0x0000000Du)
#define CSL_NAND_AB4CR_R_SETUP_RESETVAL  (0x0000000Fu)

#define CSL_NAND_AB4CR_R_STROBE_MASK     (0x00001F80u)
#define CSL_NAND_AB4CR_R_STROBE_SHIFT    (0x00000007u)
#define CSL_NAND_AB4CR_R_STROBE_RESETVAL (0x0000003Fu)

#define CSL_NAND_AB4CR_R_HOLD_MASK       (0x00000070u)
#define CSL_NAND_AB4CR_R_HOLD_SHIFT      (0x00000004u)
#define CSL_NAND_AB4CR_R_HOLD_RESETVAL   (0x00000007u)

#define CSL_NAND_AB4CR_TA_MASK           (0x0000000Cu)
#define CSL_NAND_AB4CR_TA_SHIFT          (0x00000002u)
#define CSL_NAND_AB4CR_TA_RESETVAL       (0x00000003u)

#define CSL_NAND_AB4CR_ASIZE_MASK        (0x00000003u)
#define CSL_NAND_AB4CR_ASIZE_SHIFT       (0x00000000u)
#define CSL_NAND_AB4CR_ASIZE_RESETVAL    (0x00000001u)

/*----ASIZE Tokens----*/
#define CSL_NAND_AB4CR_ASIZE_DATA8       (0x00000000u)

#define CSL_NAND_AB4CR_RESETVAL          (0x3FFFFFFDu)
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