Uint16 p16o;
    
    /** Odd Polarity for p8 */
    Uint16 p8o;
    
    /** Odd Polarity for p4 */
    Uint16 p4o;
    
    /** Odd Polarity for p2 */
    Uint16 p2o;
    
    /** Odd Polarity for p1 */
    Uint16 p1o;
    
    /** Even Polarity for p2048 */
    Uint16 p2048e;
    
    /** Even Polarity for p1028 */
    Uint16 p1024e;
    
    /** Even Polarity for p512 */
    Uint16 p512e;
    
    /** Even Polarity for p256 */
    Uint16 p256e;
    
    /** Even Polarity for p128 */
    Uint16 p128e;
    
    /** Even Polarity for p64 */
    Uint16 p64e;
    
    /** Even Polarity for p32 */
    Uint16 p32e;
    
    /** Even Polarity for p16 */
    Uint16 p16e;
    
    /** Even Polarity for p8 */
    Uint16 p8e;
    
    /** Even Polarity for p4 */
    Uint16 p4e;
    
    /** Even Polarity for p2 */
    Uint16 p2e;
    
    /** Even Polarity for p1 */
    Uint16 p1e;
}CSL_NandFlashECC;

/** @brief IODFT MISR structure
*
* This structure holds the three fields in the IODFT MISR Registers -IODFTMRLR,
* IODFTMRMR, IODFTMRMSBR.
*/
typedef struct {
    /** MISR LSB value */
    Uint32 misrLsb;
    /** MISR MID value */
    Uint32 misrMid;
    /** MISR MSB value */
    Uint32 misrMsb;
}CSL_NandIodftMisr;

/** @brief Enumeration for queries passed to @a CSL_nandGetHwStatus()
 *
 * This is used to get the status of different operations or to get the
 * existing setup of NAND.
 */
typedef enum {
    /**
     * @brief   Get the NAND module ID and revision numbers
     * (response type: @a (CSL_NandRevStatus*))
     * @param   ( )
     */
    CSL_NAND_QUERY_REV_ID_STATUS = 1,

    /**
     * @brief   Get the NAND endianness (response type: @a Uint16 *)
     * @param   ( )
     */
    CSL_NAND_QUERY_ENDIANNESS = 2,

    /**
     * @brief   Get the NAND rate information(response type: @a Uint16 *)
     * @param   ( )
     */
    CSL_NAND_QUERY_RATE = 3,

    /**
     * @brief   Get the Wait Rise Interrupt Status (response type: @a Uint16 *)
     * @param   ( )
     */
    CSL_NAND_QUERY_WR_INT_STATUS = 4,

    /**
     * @brief   Get the Line Trap Interrupt Status (response type: @a Uint16 *)
     * @param   ( )
     */
    CSL_NAND_QUERY_LT_INT_STATUS = 5,

    /**
     * @brief   Get the Asynchronous Timeout Interrupt Status
     * (response type: @a Uint16 *)
     * @param   ( )
     */
    CSL_NAND_QUERY_AT_INT_STATUS = 6,

    /**
     * @brief   Get the NAND Flash Status (response type: @a Uint16 *)
     * @param   ( )
     */
    CSL_NAND_QUERY_NAND_FLASH_STATUS = 7,

    /**
     * @brief   Read the NAND FLASH ECC for Chip select 5
     * (response type: @a (CSL_NandNandFlashECC *))
     * @param   ( )
     */
    CSL_NAND_QUERY_CS5_NAND_FLASH_ECC = 8,

    /**
     * @brief   Read the NAND FLASH ECC for Chip select 4
     * (response type: @a (CSL_NandNandFlashECC *))
     * @param   ( )
     */
    CSL_NAND_QUERY_CS4_NAND_FLASH_ECC = 9,

    /**
     * @brief   Read the NAND FLASH ECC for Chip select 3
     * (response type: @a (CSL_NandNandFlashECC *))
     * @param   ( )
     */
    CSL_NAND_QUERY_CS3_NAND_FLASH_ECC = 10,

    /**
     * @brief  Read the NAND FLASH ECC for Chip select 2
     * (response type: @a (CSL_NandNandFlashECC *))
     * @param  ( )
     */
    CSL_NAND_QUERY_CS2_NAND_FLASH_ECC = 11,

    /**
     * @brief  Read the number of cycles MISR count will be accumulated in 
     * IODFT Execution Control Register (response type : @a Uint16 *)
     * @param  ( )
     */
    CSL_NAND_QUERY_IODFT_TLEC = 12,

    /**
     * @brief  Read the MISR result signature of a given test after the 
     * download function is executed (response type : @a (CSL_NandIodftMisr *))
     * @param  ( )
     */
    CSL_NAND_QUERY_IODFT_MISR = 14,

    /**
     * @brief  Read the Release number from Module Release Number Register
     * (response type: @a Uint16 *)
     * @param  ( )
     */
    CSL_NAND_QUERY_RELEASE_NUM = 15
  } CSL_NandHwStatusQuery;

/** @brief Enumeration for queries passed to @a CSL_nandHwControl()
 *
 * This is used to select the commands to control the operations
 * existing setup of NAND. The arguments to be passed with each
 * enumeration if any are specified next to the enumeration.
 */
typedef enum {
    /**
     * @brief   Enable the Wait Rise Interrupt
     * @param   (None)
     */
    CSL_NAND_CMD_WR_ENABLE = 1,

    /**
     * @brief   Disable the Wait Rise Interrupt
     * @param   (None)
     */
    CSL_NAND_CMD_WR_DISABLE = 2,

    /**
     * @brief   Enable the Line Trap Interrupt
     * @param   (None)
     */
    CSL_NAND_CMD_LT_ENABLE = 3,

    /**
     * @brief   Disable the Line Trap Interrupt
     * @param   (None)
     */
    CSL_NAND_CMD_LT_DISABLE = 4,

    /**
     * @brief   Enable the Asynchronous Timeout Interrupt
     * @param   (None)
     */
    CSL_NAND_CMD_AT_ENABLE = 5,

    /**
     * @brief   Disable the Asynchronous Timeout Interrupt
     * @param   (None)
     */
    CSL_NAND_CMD_AT_DISABLE = 6,

    /**
     * @brief   Start ECC calculation for Chip Select 5
     * @param   (None)
     */
    CSL_NAND_CMD_CS5_ECC_START = 7,

    /**
     * @brief   Start ECC calculation for Chip Select 4
     * @param   (None)
     */
    CSL_NAND_CMD_CS4_ECC_START = 8,

    /**
     * @brief   Start ECC calculation for Chip Select 3
     * @param   (None)
     */
    CSL_NAND_CMD_CS3_ECC_START = 9,

    /**
     * @brief   Start ECC calculation for Chip Select 2
     * @param   (None)
     */
    CSL_NAND_CMD_CS2_ECC_START = 10,

    /**
     * @brief   Enable the CS5 NAND FLASH
     * @param   (None)
     */
    CSL_NAND_CMD_CS5_NAND_ENABLE = 11,

    /**
     * @brief   Disable the CS5 NAND FLASH
     * @param   (None)
     */
    CSL_NAND_CMD_CS5_NAND_DISABLE = 12,

    /**
     * @brief   Enable the CS4 NAND FLASH
     * @param   (None)
     */
    CSL_NAND_CMD_CS4_NAND_ENABLE = 13,

    /**
     * @brief   Disable the CS4 NAND FLASH
     * @param   (None)
     */
    CSL_NAND_CMD_CS4_NAND_DISABLE = 14,

    /**
     * @brief   Enable the CS3 NAND FLASH
     * @param   (None)
     */
    CSL_NAND_CMD_CS3_NAND_ENABLE = 15,

    /**
     * @brief   Disable the CS3 NAND FLASH
     * @param   (None)
     */
    CSL_NAND_CMD_CS3_NAND_DISABLE = 16,

    /**
     * @brief   Enable the CS2 NAND FLASH
     * @param   (None)
     */
    CSL_NAND_CMD_CS2_NAND_ENABLE = 17,

    /**
     * @brief   Disable the CS2 NAND FLASH
     * @param   (None)
     */
    CSL_NAND_CMD_CS2_NAND_DISABLE = 18,

    /**
     * @brief   Set the MISR counter
     * @param   (Uint16*)
     */
    CSL_NAND_CMD_IODFT_SET_TLEC = 19,

    /**
     * @brief   Set the MISR trigger on
     * @param   (Uint16*)
     */
    CSL_NAND_CMD_IODFT_MISR_ON = 20,

    /**
     * @brief   Set the MISR trigger off
     * @param   (None)
     */
    CSL_NAND_CMD_IODFT_MISR_OFF = 21,

    /**
     * @brief   Load the pattern generators initial value
     * @param   (None)
     */
    CSL_NAND_CMD_IODFT_OPGLD = 22,

    /**
     * @brief   Set the MISR input source as output register
     * @param   (None)
     */
    CSL_NAND_CMD_IODFT_MMS_OP_REG = 23,

    /**
     * @brief   Set the MISR input source as input capture
     * @param   (None)
     */
    CSL_NAND_CMD_IODFT_MMS_INP_CAP = 24,

    /**
     * @brief   Set the test mode for Output enable select
     */
    CSL_NAND_CMD_IODFT_ESEL_TEST = 25,

    /**
     * @brief   Set the normal mode for Output enable select
     */
    CSL_NAND_CMD_IODFT_ESEL_NORMAL = 26,

    /**
     * @brief   Enable the output for Test Output Enable Control
     * @param   (None)
     */
    CSL_NAND_CMD_IODFT_TOEN_ENABLE = 27,

    /**
     * @brief   Disable the output for Test Output Enable Control
     * @param   (None)
     */
    CSL_NAND_CMD_IODFT_TOEN_DISABLE = 28,

    /**
     * @brief   Set the MISR state
     * @param   (Uint16*)
     */
    CSL_NAND_CMD_IODFT_SET_MISR_STATE = 29,

    /**
     * @brief   Set the Pattern code
     * @param   (Uint16*)
     */
    CSL_NAND_CMD_IODFT_SET_PATTERN_CODE = 30,

    /**
     * @brief   Set the IODFT to functional mode
     * @param   (None)
     */
    CSL_NAND_CMD_IODFT_FUNC_MODE = 31,

    /**
     * @brief   Set to IODFT mode
     * @param   (None)
     */
    CSL_NAND_CMD_IODFT_MODE = 32
} CSL_NandHwControlCmd;


/**************************************************************************\
* NAND global function declarations
\**************************************************************************/

/*
 * ============================================================================
 *   @func CSL_nandInit
 *
 *   @desc
 *        This function is idempotent in that calling it many times is same as
 *        calling it once. This function initializes the NAND CSL data 
 *        structures.
 *
 *   @arg pContext
 *        Context information for NAND
 *
 *   @ret CSL_Status
 *        CSL_SOK - Always returns
 *
 *   @eg
 *     CSL_nandInit (&pContext);
 * ============================================================================
 */
CSL_Status  CSL_nandInit(
    CSL_NandContext * pContext
);


/** ============================================================================
 *   @n@b CSL_nandOpen
 *
 *   @b Description
 *   @n This function populates the peripheral dnand object for the NAND instance
 *        and returns a handle to the instance.
 *      The open call sets up the dnand structures for the particular instance
 *        of NAND device. The device can be re-opened anytime after it has been
 *      normally closed if so required. The handle returned by this call is
 *      input as an essential argument for rest of the APIs described
 *      for this module.
 *
 *   @b Arguments
 *   @verbatim
              pNandObj      Pointer to the NAND instance object