/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005                 
 *                                                                              
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.             
 *   ===========================================================================
 */ 

/** @file csl_emif.h
 *
 *  @brief    Header file for functional layer of CSL
 *
 *    Path: \\(CSLPATH)\\ipmodules\\emifs\\src
 *
 * Description
 *    - The different enumerations, structure definitions
 *      and function declarations
 *
 * Modification 1
 *    - Created on: 10/6/2004
 *    - Reason: created the sources
 *
 * @date 10th June, 2004
 * @author Santosh Narayanan.
 *
 */

/** @mainpage EMIF CSL 3.x
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs for
 * the EMIF module across various devices. The CSL developer is expected to
 * refer to this document while designing APIs for these modules. Some of the
 * listed APIs may not be applicable to a given EMIF module. While other cases
 * this list of APIs may not be sufficient to cover all the features of a
 * particular EMIF Module. The CSL developer should use his discretion designing
 * new APIs or extending the existing ones to cover these.
 *
 * @subsection aaa Terms and Abbreviations
 *   -# CSL:  Chip Support Library
 *   -# API:  Application Programmer Interface
 *
 * @subsection References
 *    -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02
 *    -# EMIF_SPEC, EMIF Module Specifications DocumentVersion 2.1.2
 *
 */

/* =============================================================================
 *  Revision History
 *  ===============
 *  27-Aug-2004  brn      Updated for the new CSL architecture
 *  11-Oct-2004  brn      Updated with the code review comments.
 *                        Added header for CSL_pwmInit() function.
 * =============================================================================
 */

#ifndef _CSL_EMIF_H_
#define _CSL_EMIF_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <cslr.h>
#include <soc.h>
#include <csl_error.h>
#include <csl_types.h>
#include <cslr_emif.h>


/**************************************************************************\
* EMIF global macro declarations
\**************************************************************************/

/** Constants for passing parameters to the EMIF HwSetup function.
 */

/** For disabling the Self Refresh mode of SDRAM          */
#define CSL_EMIF_SELF_REFRESH_DISABLE                   (0)

/** For enabling the Self Refresh mode of SDRAM           */
#define CSL_EMIF_SELF_REFRESH_ENABLE                    (1)

/** For disabling the Power down mode of SDRAM           */
#define CSL_EMIF_POWER_DOWN_DISABLE                     (0)

/** For enabling the Power down mode of SDRAM           */
#define CSL_EMIF_POWER_DOWN_ENABLE                      (1)

/** For disabling the Refresh during Power down mode of SDRAM  */

#define CSL_EMIF_PDWR_DISABLE                           (0)

/** For enabling the Refresh during Power down mode of SDRAM  */
#define CSL_EMIF_PDWR_ENABLE                            (1)

/** For disabling the SDRAM narrow mode */
#define CSL_EMIF_NM_DISABLE                             (0)

/** For enabling the SDRAM narrow mode */
#define CSL_EMIF_NM_ENABLE                              (1)

/** For disabling the DLL select for DDR1 SDRAM  */
#define CSL_EMIF_DDR_DLL_DISABLE                        (1)

/** For enabling the DLL select for DDR1 SDRAM  */
#define CSL_EMIF_DDR_DLL_ENABLE                         (0)

/** For de-selecting Strobe mode for Async banks */
#define CSL_EMIF_ASYNC_SS_DISABLE                       (0)

/** For selecting Strobe mode for Async banks */
#define CSL_EMIF_ASYNC_SS_ENABLE                        (1)

/** For disabling the Extended Wait mode for Async banks */
#define CSL_EMIF_ASYNC_EW_DISABLE                       (0)

/** For enabling the Extended Wait mode for Async banks */
#define CSL_EMIF_ASYNC_EW_ENABLE                        (1)

/** For disabling the TAPV field of DDR PHY Control Register */
#define CSL_EMIF_DDR_TAPV_DISABLE                       (0)

/** For enabling the TAPV field of DDR PHY Control Register */
#define CSL_EMIF_DDR_TAPV_ENABLE                        (1)

/** For disabling NAND FLASH on chip select 5 */
#define CSL_EMIF_CS5_NAND_DISABLE                       (0)

/** For enabling NAND FLASH on chip select 5 */
#define CSL_EMIF_CS5_NAND_ENABLE                        (1)

/** For disabling NAND FLASH on chip select 4 */
#define CSL_EMIF_CS4_NAND_DISABLE                       (0)

/** For enabling NAND FLASH on chip select 4 */
#define CSL_EMIF_CS4_NAND_ENABLE                        (1)

/** For disabling NAND FLASH on chip select 3 */
#define CSL_EMIF_CS3_NAND_DISABLE                       (0)

/** For enabling NAND FLASH on chip select 3 */
#define CSL_EMIF_CS3_NAND_ENABLE                        (1)

/** For disabling NAND FLASH on chip select 2 */
#define CSL_EMIF_CS2_NAND_DISABLE                       (0)

/** For enabling NAND FLASH on chip select 2 */
#define CSL_EMIF_CS2_NAND_ENABLE                        (1)

/** Default wait Polarity low */
#define CSL_EMIF_WAIT_POLARITY_LOW                      (0)

/* These are the definitions for Deafault Hwsetup function */
/* Default wait Polarity high */
#define CSL_EMIF_WAIT_POLARITY_HI                       (1)

/* Chip Selsct low */
#define CSL_EMIF_CHIP_SEL_LOW                           (0)

/* Chip Selsct High */
#define CSL_EMIF_CHIP_SEL_HI                            (1)

/* Default max wait */
#define CSL_EMIF_MAX_WAIT                               (0x80)

/* Default DDR refresh threshold */
#define CSL_EMIF_REFRESH_TRESH                          (0)

/* Default value for write setup cycles hold */
#define CSL_EMIF_WRITE_SETUP                            (0xf)

/* Default refresh rate */
#define CSL_EMIF_REF_RATE                               (16)

/* Default value for write hold */
#define CSL_EMIF_WRITE_HOLD                             (0x3f)

/* Default value for read setup cycles hold */
#define CSL_EMIF_READ_SETUP                             (7)

/* Default value for read hold */
#define CSL_EMIF_READ_HOLD                              (3)

/* Default value for train */
#define CSL_EMIF_TRAIN                                  (0xFFFF)

/* Default Async size */
#define CSL_EMIF_ASYN_SIZE                              (1)



/**************************************************************************\
* EMIF global typedef declarations
\**************************************************************************/

/** @brief This Object contains the reference to the instance of EMIF opened
 *  using the @a CSL_emifOpen().
 *
 *  The pointer to this, is passed to all EMIF CSL APIs.
 */
typedef struct CSL_EmifObj {
    /** This is a pointer to the registers of the instance of EMIF
     *  referred to by this object
     */
    CSL_EmifRegsOvly  regs;

    /** This is the instance of EMIF being referred to by this object  */
    CSL_InstNum perNum;

}CSL_EmifObj;

/** @brief this is a pointer to @a CSL_EmifObj and is passed as the first
 *  parameter to all EMIF CSL APIs
 */
typedef struct CSL_EmifObj *CSL_EmifHandle;

/** @brief SDRAM Configuration structure.
 *
 * All fields needed for SDRAM Bank configuration are present in this structure.
 */
typedef struct {
    /** Self Refresh mode: 0==> No refresh, 1==> Self Refresh*/
    Uint16 selfRefresh;

    /** Power down mode: 0==> No power down, 1==> Power down mode */
    Uint16 powerDown;

    /** Power down with Refresh: 0==> No Autorefresh, 1==> Exit power down and
     * perform autorefresh
     */
    Uint16 pdwr;

    /**  EMIF data bus width: 0==> 32 bit, 1==> 16 bit   */
    Uint16 narrowMode;

    /** Disable DLL for DDR SDRAM: 0==> Enable, 1==> Disable */
    Uint16 disableDdrDll;

    /** Bit 13 Enable: 0==> Disable Bit 13, 1==> Enable Bit 13 */
    Uint16 bit13Enable;

    /** CAS Latency */
    Uint16 casLatency;

    /** Bit 9-11 Enable: 0==> Disable, 1==> Enable */
    Uint16 bit911Enable;

    /** Number of Internal SDRAM banks */
    Uint16 intBank;

    /** External SDRAM bank Setup: 0==>CS0 used for SDRAM,
     * 1==>CS0 & CS1 used for SDRAM
     */
    Uint16 extBank;

    /** Page Size of the internal SDRAM devices: 0==>256-word, 1==> 512-word,
     *  2==>1024-word, 3==>2048-word
     */
    Uint16 pageSize;

} CSL_EmifSdramConfig;

/** @brief SDRAM Refresh Control structure.
 *
 * All fields needed for SDRAM Refresh control are present in this structure.
 */
typedef struct {
    /** DDR Refresh Threshold */
    Uint16 ddrRefreshThresh;

    /** Refresh Rate */
    Uint16 refreshRate;

} CSL_EmifSdramRefreshControl;

/** @brief SDRAM Timing structure.
 *
 * All fields needed for SDRAM Timing are present in this structure.
 */
typedef struct {
    /** Specifies TRFC value: Minimum number of EMIF cycles from Refresh or
     *  Load command to Refresh or Activate command, minus one
     */
    Uint16 trfc;

    /** Specifies TRP value: Minimum number of EMIF cycles from Pre-charge to
     *  Active or Refresh command, minus one
     */
    Uint16 trp;

    /** Specifies TRCD value: Minimum number of EMIF cycles from Active to
     *  Read or Write command, minus one
     */
    Uint16 trcd;

    /** Specifies TWR value: Minimum number of EMIF cycles from last write
     *  transfer to Pre-charge command, minus one
     */
    Uint16 twr;

    /** Specifies TRAS value: Minimum number of EMIF cycles from Activate to
     *  Pre-charge command, minus one
     */
    Uint16 tras;

    /** Specifies TRC value: Minimum number of EMIF cycles from Activate
     *  command to Activate command, minus one
     */
    Uint16 trc;

    /** Specifies TRRD value: Minimum number of EMIF cycles from Activate
     *   command to Activate command for a differnt bank, minus one
     */
    Uint16 trrd;

    /** Specifies the minimum number of EMIF clock cycles from Self refresh
     *  exit to any command, minus one
     */
    Uint16 txs;

} CSL_EmifSdramTiming;

/** @brief Asynchronous Wait Cycle Configuration structure
 *
 * All fields needed for Async Wait Cycle configuration are present in this structure.
 */
typedef struct {
    /** Wait polarity for pad_wait_i[3]*/
    Uint16 wp3;

    /** Wait polarity for pad_wait_i[2]*/
    Uint16 wp2;

    /** Wait polarity for pad_wait_i[1]*/
    Uint16 wp1;

    /** Wait polarity for pad_wait_i[0]*/
    Uint16 wp0;

    /** pad_wait_i map bits for chip select 5 */
    Uint16 cs3Wait;

    /** pad_wait_i map bits for chip select 4 */
    Uint16 cs2Wait;

    /** pad_wait_i map bits for chip select 3 */
    Uint16 cs1Wait;

    /** pad_wait_i map bits for chip select 2 */
    Uint16 cs0Wait;

    /** Maximum external wait cycles */
    Uint16 maxExtWait;

} CSL_EmifAsyncWaitCycleConfig;

/** @brief Asynchronous Bank Configuration structure
 *
 * All fields needed for async bank configuration are present in this structure.
 */
typedef struct {
    /** Select strobe mode */
    Uint16 selectStrobe;

    /** Extend wait mode */
    Uint16 extWait;

    /** Write strobe setup cycles */
    Uint16 writeSetup;

    /** Write strobe duration cycles */
    Uint16 writeStrobe;

    /** Write strobe hold cycles */
    Uint16 writeHold;

    /** Read strobe setup cycles */
    Uint16 readSetup;

    /** Read strobe duration cycles */
    Uint16 readStrobe;

    /** Read strobe hold cycles */
    Uint16 readHold;

    /** Turnaround cycles */
    Uint16 turnAround;

    /** Asyncronous Bank size */
    Uint16 asyncSize;

} CSL_EmifAsyncBankConfig;

/** @brief  DDR PHY Control Register structure
 *
 *  All fields needed for DDR PHY Control are present in this structure.
 */
typedef struct {
    /** Enable the TAP values for the EMIF Retiming manager */
    Uint16 tapvEnable;

    /** TAP value */
    Uint16 tapv;

    /** RTM PHY training time */
    Uint16 train;

} CSL_EmifDdrPhyControl;

/** @brief  NAND FLASH Control Register structure
 *
 *  All fields needed for NAND FLASH Control are present in this structure.
 */
typedef struct {
    /** Chip select 5 Nand */
    Uint16 cs5nand;

    /** Chip select 4 Nand */
    Uint16 cs4nand;

    /** Chip select 3 Nand */
    Uint16 cs3nand;

    /** Chip select 2 Nand */
    Uint16 cs2nand;

} CSL_EmifNandFlashControl;

/** @brief This has all the fields required to configure EMIF at Power Up
 *  (After a Hardware Reset) or a Soft Reset
 *
 *  This structure is used to setup or obtain existing setup of
 *  EMIF using @a CSL_emifHwSetup() & @a CSL_emifGetHwSetup() functions
 *  respectively.
 */
typedef struct {
    /** Structure for Async Wait Cycle configuration */
    CSL_EmifAsyncWaitCycleConfig  asyncWaitCycleConfig;

    /** Structure for SDRAM Refresh control */
    CSL_EmifSdramRefreshControl emifSdramRefreshControl;

    /** Structure for SDRAM Timing */
    CSL_EmifSdramTiming sdramTiming;

    /** Structure for SDRAM Bank configuration */
    CSL_EmifSdramConfig sdramBankConfig;

    /** Structure for Async Bank 1 Config Registers */
    CSL_EmifAsyncBankConfig asyncBank1Config;

    /** Structure for Async Bank 2 Config Registers */
    CSL_EmifAsyncBankConfig asyncBank2Config;

    /** Structure for Async Bank 3 Config Registers */
    CSL_EmifAsyncBankConfig asyncBank3Config;

    /** Structure for Async Bank 4 Config Registers */
    CSL_EmifAsyncBankConfig asyncBank4Config;

    /** Structure for DDR PHY control */
    CSL_EmifDdrPhyControl ddrPhyControl;

    /** Structure for NAND FLASH control */
    CSL_EmifNandFlashControl nandFlashControl;

} CSL_EmifHwSetup;

/** @brief EMIF Module ID and Revision structure
 *
 *  This structure is used for querying the EMIF module ID and revision
 */
typedef struct {
    /** EMIF Module ID */
    Uint16 moduleID;

    /** EMIF Major Revision */
    Uint16 majorRev;