/* Define Parallel port register */
#define PORTADDRESS 0x378  /* Enter Your Port Address Here */
#define IRQ 7              /* IRQ Here */

#define DATAPORT     PORTADDRESS + 0x00
#define STATUSPORT   PORTADDRESS + 0x01
#define CONTROLPORT  PORTADDRESS + 0x02
#define EPPADDPORT   PORTADDRESS + 0x03
#define EPPDATPORT   PORTADDRESS + 0x04
#define ECRPORT	     PORTADDRESS + 0x402

/* Define SMC control line */
#define CLE          7    // 1: Command   0: Data or Address
#define CE_N         6	  // 1: Inactive  0: Active
#define ALE          5    // 1: Address   0: Data
#define WP_N         4	  // 1: Writable  0: Unwritable
#define SMCPWR       3	  // 1: Power off 0: Power on

#define CLE_CTRL      0x80 // 1: Command   0: Data or Address
#define CE_CTRL       0x40 // 1: Inactive  0: Active
#define ALE_CTRL      0x20 // 1: Address   0: Data
#define WP_CTRL       0x10 // 1: Writable  0: Unwritable
#define SMCPWR_CTRL   0x08 // 1: Power off 0: Power on
#define CD_STATUS     0x20 // 1: Remove    0: Inserted
#define BUSY_STATUS   0x40 // 1: Busy      0: Ready
#define READER_STATUS 0x08 // Reader status

#define PASS	   1
#define FAIL       2
#define ECCERROR   3
/* Define SMC access command */
#define Serial_Data_Input_cmd      0x80		// Serial data input
#define Read1_cmd    		   0x00		// Read Mode (1) Address Pointer: 0   --- 255
#define Read2_cmd    		   0x01		// Read Mode (2) Address Pointer: 256 --- 511
#define Read3_cmd        	   0x50	  	// Read Mode (3) Address Pointer: 512 --- 527
#define Reset_cmd    		   0xff
#define Page_Program_True_cmd  	   0x10
#define Page_Program_Dummy_cmd 	   0x11
#define Page_Program_Multi_cmd 	   0x15		// Auto Program (Multi Block Programm)
#define Block_Erase_cmd   	   0x60
#define Block_Erase_Confirm_cmd    0xd0
#define Read_Status1_cmd   	   0x70
#define Read_Status2_cmd   	   0x71
#define ReadID1_cmd   		   0x90
#define ReadID2_cmd   		   0x91

/***************************************************************************/
#define Hw_InData() inp(EPPDATPORT)
#define Hw_OutData(a) outp(EPPDATPORT,(a))
/*****/
#define Hw_VccOn()  {hwcontrol_status &= ~SMCPWR_CTRL; outp(EPPADDPORT,hwcontrol_status);}
#define Hw_VccOff() {hwcontrol_status |= SMCPWR_CTRL; outp(EPPADDPORT,hwcontrol_status);}
/*****/
#define Hw_chip_enable()  {hwcontrol_status &= ~CE_CTRL; outp(EPPADDPORT,hwcontrol_status);}
#define Hw_chip_disable() {hwcontrol_status |= CE_CTRL; outp(EPPADDPORT,hwcontrol_status);}
/*****/
#define Hw_write_enable()  {hwcontrol_status |= WP_CTRL; outp(EPPADDPORT,hwcontrol_status);}
#define Hw_write_disable() {hwcontrol_status &= ~WP_CTRL; outp(EPPADDPORT,hwcontrol_status);}
/*****/
#define Hw_add_latch_enable() {hwcontrol_status |= ALE_CTRL; outp(EPPADDPORT,hwcontrol_status);}
#define Hw_add_latch_disable() {hwcontrol_status &= ~ALE_CTRL; outp(EPPADDPORT,hwcontrol_status);}
/*****/
#define Hw_cmd_latch_enable() {hwcontrol_status |= CLE_CTRL; outp(EPPADDPORT,hwcontrol_status);}
#define Hw_cmd_latch_disable() {hwcontrol_status &= ~CLE_CTRL; outp(EPPADDPORT,hwcontrol_status);}

/*****/
#define Hw_ReadStatus() (inp(STATUSPORT) & 0x60)
#define Hw_ChkCardIn() (inp(STATUSPORT) & CD_STATUS)   // 0x20: inserted  0x00: Removed
#define Hw_ChkBusy() (inp(STATUSPORT) & BUSY_STATUS)   // 0x40: BUSY      0x00: Ready