/* s3c2510.h - SAMSUNG S3C2510 header file */

/* Copyright 2002 SAMSUNG ELECTRONICS */

/*
modification history
--------------------
01b,10July02,jwchoi
01a,08feb02,jmLee created.
*/


#ifndef INCs3c2510h
#define INCs3c2510h

#ifdef  __cplusplus
extern  "C" {
#endif


#ifndef S3C2510ABBREVIATIONS
#define S3C2510ABBREVIATIONS

#ifdef   _ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
typedef volatile UCHAR VCHAR;                               /* shorthand for volatile UCHAR */
typedef volatile INT32 VINT32;                              /* volatile unsigned word */
typedef volatile INT16 VINT16;                              /* volatile unsigned halfword */
typedef volatile INT8 VINT8;                                /* volatile unsigned byte */
typedef volatile UINT32 VUINT32;                            /* volatile unsigned word */
typedef volatile UINT16 VUINT16;                            /* volatile unsigned halfword */
typedef volatile UINT8 VUINT8;                              /* volatile unsigned byte */
#define CAST(x) (x)
#endif  /* _ASMLANGUAGE */

#endif /* S3C2510ABBREVIATIONS */


/* S3C2510 ASIC Base Address */

#define S3C2510_REG_BASE_ADRS           0xF0000000          /* Internal Register Base Address */
#define S3C2510_REG_SIZE                0x00200000          /* Internal Register Size */

#define REG_32(_off)                    (CAST(VUINT32 *)(S3C2510_REG_BASE_ADRS + _off))
#define REG_16(_off)                    (CAST(VUINT16 *)(S3C2510_REG_BASE_ADRS + _off))
#define REG_8(_off)                     (CAST(VUINT8  *)(S3C2510_REG_BASE_ADRS + _off))


/*******************************************************************************
        S3C2510 System Configuration Special Registers
*******************************************************************************/

#define S3C2510_SYSCFG                  REG_32(0x00000000)  /* System Configuration Register */
#define S3C2510_PDCODE                  REG_32(0x00000004)  /* Product Code and Revision Number Register */
#define S3C2510_MISCREG                 REG_32(0x00000008)  /* System Clock Control Register */
#define S3C2510_PCLKDIS                 REG_32(0x0000000C)  /* Peripheral Clock Disable Register */
#define S3C2510_CLKST                   REG_32(0x00000010)  /* Clock Status Register */
#define S3C2510_HPRIF                   REG_32(0x00000014)  /* AHB Bus Master Fixed Priority Register */
#define S3C2510_HPRIR                   REG_32(0x00000018)  /* AHB Bus Master Round-Robin Priority Register */
#define S3C2510_CPLLCON                 REG_32(0x0000001C)  /* Core PLL Configuration Register */
#define S3C2510_SPLLCON                 REG_32(0x00000020)  /* System PLL Configuration Register */
#define S3C2510_UPLLCON                 REG_32(0x00000024)  /* USB PLL Configuration Register */
#define S3C2510_PPLLCON                 REG_32(0x00000028)  /* PHY PLL Configuration Register */

/* System Configuration Register Bit Definitions */

#define S3C2510_SYSCFG_CPLLREN          0x80000000          /* CPLLCON Register Enable */
#define S3C2510_SYSCFG_SPLLREN          0x40000000          /* SPLLCON Register Enable */
#define S3C2510_SYSCFG_UPLLREN          0x20000000          /* UPLLCON Register Enable */
#define S3C2510_SYSCFG_PPLLREN          0x10000000          /* PPLLCON Register Enable */
#define S3C2510_SYSCFG_CPLLCE           0x08000000          /* CPLL Clock Enable during Configuration */
#define S3C2510_SYSCFG_SPLLCE           0x04000000          /* SPLL Clock Enable during Configuration */
#define S3C2510_SYSCFG_UPLLCE           0x02000000          /* UPLL Clock Enable during Configuration */
#define S3C2510_SYSCFG_PPLLCE           0x01000000          /* PPLL Clock Enable during Configuration */
#define S3C2510_SYSCFG_BIG              0x00010000          /* Big Endian */
#define S3C2510_SYSCFG_REMAP            0x00000100          /* Remap Enable */
#define S3C2510_SYSCFG_HCLKODIS         0x00000010          /* HCLKO Output Disable */
#define S3C2510_SYSCFG_ARBR             0x00000002          /* Round-Robin Priority */
#define S3C2510_SYSCFG_ARBF             0x00000001          /* Fixed Priority */
#define S3C2510_SYSCFG_ARBC             0x00000000          /* Conventional Round-Robin Priority.
															   All bus master can get the bus equally. */

/* Product Code and Revision Number Register Bit Definitions */

#define S3C2510_PDCODE_PC_MASK          0xFFFF0000          /* Product Code */
#define     S3C2510_PDCODE_PC_SHIFT         16
#define S3C2510_PDCODE_MAJ_REV_MASK     0x000000F0          /* Major Revision Number */
#define     S3C2510_PDCODE_MAJ_REV_SHIFT    4               /* Major Revision Number */
#define S3C2510_PDCODE_MIN_REV_MASK     0x0000000F          /* Minor Revision Number */
#define     S3C2510_PDCODE_MIN_REV_SHIFT    0

/* System Clock Control Register */

#define S3C2510_CLKCON_DVAL_MASK        0x0000FFFF          /* System Clock Dividing Clock */
#define     S3C2510_CLKCON_DIV_1            0x00000000      /* Divide by     1 */
#define     S3C2510_CLKCON_DIV_2            0x00000001      /* Divide by     2 */
#define     S3C2510_CLKCON_DIV_3            0x00000002      /* Divide by     3 */
#define     S3C2510_CLKCON_DIV_5            0x00000004      /* Divide by     5 */
#define     S3C2510_CLKCON_DIV_9            0x00000008      /* Divide by     9 */
#define     S3C2510_CLKCON_DIV_17           0x00000010      /* Divide by    17 */
#define     S3C2510_CLKCON_DIV_33           0x00000020      /* Divide by    33 */
#define     S3C2510_CLKCON_DIV_65           0x00000040      /* Divide by    65 */
#define     S3C2510_CLKCON_DIV_129          0x00000080      /* Divide by   129 */
#define     S3C2510_CLKCON_DIV_257          0x00000100      /* Divide by   257 */
#define     S3C2510_CLKCON_DIV_513          0x00000200      /* Divide by   513 */
#define     S3C2510_CLKCON_DIV_1025         0x00000400      /* Divide by  1025 */
#define     S3C2510_CLKCON_DIV_2049         0x00000800      /* Divide by  2049 */
#define     S3C2510_CLKCON_DIV_4097         0x00001000      /* Divide by  4097 */
#define     S3C2510_CLKCON_DIV_8193         0x00002000      /* Divide by  8193 */
#define     S3C2510_CLKCON_DIV_16385        0x00004000      /* Divide by 16385 */
#define     S3C2510_CLKCON_DIV_32769        0x00008000      /* Divide by 32769 */

/* Peripheral Clock Disable Register Bit Definitions. If set to one, disable corresponding block. */

#define S3C2510_PCLKDIS_SRREQ           0x80000000          /* SDRAM Self Refresh Request */
#define S3C2510_PCLKDIS_SRACK           0x40000000          /* SDRAM Self Refresh Acknowedge(Read Only) */
#define S3C2510_PCLKDIS_SAR		        0x04000000          /* SAR_UTOPIA Clock Disable */
#define S3C2510_PCLKDIS_PCI_PCCARD      0x02000000          /* PCI/PCCard Clock Disable */
#define S3C2510_PCLKDIS_USBH	        0x01000000          /* USB Host Clock Disable */
#define S3C2510_PCLKDIS_SDRAM           0x00800000          /* SDRAM Clock Disable */
#define S3C2510_PCLKDIS_MEMCON          0x00400000          /* MEMCON Clock Disable */
#define S3C2510_PCLKDIS_DES             0x00200000          /* DES Clock Disable */
#define S3C2510_PCLKDIS_I2C             0x00100000          /* I2C Clock Disable */
#define S3C2510_PCLKDIS_IOP             0x00080000          /* IOP Clock Disable */
#define S3C2510_PCLKDIS_WDT             0x00040000          /* Watch Dog Timer Clock Disable */
#define S3C2510_PCLKDIS_TIMER5          0x00020000          /* TIMER 5 Clock Disable */
#define S3C2510_PCLKDIS_TIMER4          0x00010000          /* TIMER 4 Clock Disable */
#define S3C2510_PCLKDIS_TIMER3          0x00008000          /* TIMER 3 Clock Disable */
#define S3C2510_PCLKDIS_TIMER2          0x00004000          /* TIMER 2 Clock Disable */
#define S3C2510_PCLKDIS_TIMER1          0x00002000          /* TIMER 1 Clock Disable */
#define S3C2510_PCLKDIS_TIMER0          0x00001000          /* TIMER 0 Clock Disable */
#define S3C2510_PCLKDIS_HUART1          0x00000800          /* HUART 1 Clock Disable */
#define S3C2510_PCLKDIS_HUART0          0x00000400          /* HUART 0 Clock Disable */
#define S3C2510_PCLKDIS_CUART           0x00000200          /* CUART Clock Disable */
#define S3C2510_PCLKDIS_USB             0x00000100          /* USB Target(Device)Clock Disable */
#define S3C2510_PCLKDIS_ETH1            0x00000080          /* ETHER 1 Clock Disable */
#define S3C2510_PCLKDIS_ETH0            0x00000040          /* ETHER 0 Clock Disable */
#define S3C2510_PCLKDIS_GDMA5           0x00000020          /* GDMA 5 Clock Disable */
#define S3C2510_PCLKDIS_GDMA4           0x00000010          /* GDMA 4 Clock Disable */
#define S3C2510_PCLKDIS_GDMA3           0x00000008          /* GDMA 3 Clock Disable */
#define S3C2510_PCLKDIS_GDMA2           0x00000004          /* GDMA 2 Clock Disable */
#define S3C2510_PCLKDIS_GDMA1           0x00000002          /* GDMA 1 Clock Disable */
#define S3C2510_PCLKDIS_GDMA0           0x00000001          /* GDMA 0 Clock Disable */

/* Clock Status Register Bit Definitions */

#define S3C2510_CLKST_MODE_MASK         0xC0000000          /* Clock Mode */
#define     S3C2510_CLKST_MODE_FASTBUS      0x00000000      /* FastBus Mode */
#define     S3C2510_CLKST_MODE_SYNC         0x40000000      /* Synchronous Mode */
#define     S3C2510_CLKST_MODE_SYNC1	    0x80000000      /* In fact, it is Sync Mode */
#define     S3C2510_CLKST_MODE_ASYNC        0xC0000000      /* Asynchronous Mode */
#define S3C2510_CLKST_BUSFREQ_MASK      0x00FFF000          /* System Bus Clock Frequency, BCD */
#define S3C2510_CLKST_CPUFREQ_MASK      0x00000FFF          /* CPU Clock Frequency, BCD */

/* PLL Control Register Bit Definitions */

#define S3C2510_PLL_S_MASK              0x00030000          /* Scaler */
#define     S3C2510_PLL_S_SHIFT             16
#define S3C2510_PLL_P_MASK              0x00003F00          /* Pre Divider */
#define     S3C2510_PLL_P_SHIFT             8
#define S3C2510_PLL_M_MASK              0x000000FF          /* Main Vivider */
#define     S3C2510_PLL_M_SHIFT             0


/*******************************************************************************
        S3C2510 External I/O Bank Controller Special Registers
*******************************************************************************/

#define S3C2510_B0CON                   REG_32(0x00010000)  /* Bank 0 Control Register */
#define S3C2510_B1CON                   REG_32(0x00010004)  /* Bank 1 Control Register */
#define S3C2510_B2CON                   REG_32(0x00010008)  /* Bank 2 Control Register */
#define S3C2510_B3CON                   REG_32(0x0001000C)  /* Bank 3 Control Register */
#define S3C2510_B4CON                   REG_32(0x00010010)  /* Bank 4 Control Register */
#define S3C2510_B5CON                   REG_32(0x00010014)  /* Bank 5 Control Register */
#define S3C2510_B6CON                   REG_32(0x00010018)  /* Bank 6 Control Register */
#define S3C2510_B7CON                   REG_32(0x0001001C)  /* Bank 7 Control Register */
#define S3C2510_MUXBCON                 REG_32(0x00010020)  /* Muxed Bus Control Register */