MEMORY   
{
  PAGE 0:
      /* memory mapped registers */
      MMR_RESERVED: origin= 0x00000, length= 0x000BF
      
      /* On-chip Dual Access RAM. */
      /* Actual devices have different amounts of DARAM */
      /* and divide it into different amounts & sizes of */
      /* independent blocks. */
      
      DARAM00 (RWX) : origin = 0000400h length = 003C00h   /* sec1 - even start addr */
      DARAM01 (RWX) : origin = 0004003h length = 003FFDh   /* sec3 - odd start addr  */
      DARAM10 (RWX) : origin = 0008000h length = 004000h
      DARAM11 (RWX) : origin = 000C000h length = 004000h
    
      /* On-chip Single Access RAM. */
      /* Actual devices have different amounts of DARAM */
      /* and divide it into different amounts & sizes of */
      /* independent blocks. */

      SARAM00 (RWX) : origin = 0010000h length = 004000h
      SARAM01 (RWX) : origin = 0014000h length = 004000h   /* sec2 - even start addr */
      SARAM10 (RWX) : origin = 0018000h length = 004000h
      SARAM11 (RWX) : origin = 001C000h length = 004000h   /* sec4 - odd start addr  */

      
     
 
      /* Off-chip memory - addressed by 4 chip selects */
      EXTERNAL_CE0(RWX ): origin= 0x050000, length= 0x3B0000 
      EXTERNAL_CE1(RWX ): origin= 0x400000, length= 0x400000 
      EXTERNAL_CE2(RWX ): origin= 0x800000, length= 0x400000 
      EXTERNAL_CE3(RWX ): origin= 0xC00000, length= 0x3F8000
 
      /* On-chip 32Kx8 ROM */
      /* Last 256 byte of 32Kx8 ROM is power up default*/
      /* interrupt vector table */
      PDROM       (RWX ): origin= 0xFF8000, length= 0x7F00  
      VECTORS     (RWX ): origin= 0xFFFF00, length= 0x100 
      
}
 





SECTIONS
{  
   .text     : > SARAM10
   .data     : > SARAM10
   .bss      : > SARAM10
   
   .sec1     : > DARAM00
   .sec2     : > SARAM01
   .sec3     : > DARAM01
   .sec4     : > SARAM11
   stack     : > DARAM11
   sstack    : > DARAM11 
}