?? c8051f020.h
字號:
/*---------------------------------------------------------------------------
; Copyright (C) 2001 CYGNAL INTEGRATED PRODUCTS, INC.
; All rights reserved.
;
;
; FILE NAME : C8051F020.H
; TARGET MCUs : C8051F020, 'F021, 'F022, 'F023
; DESCRIPTION : Register/bit definitions for the C8051F02x product family.
;
; REVISION 1.1
;
;---------------------------------------------------------------------------*/
/* BYTE Registers */
sfr P0 = 0x80; /* PORT 0 */
sfr SP = 0x81; /* STACK POINTER */
sfr DPL = 0x82; /* DATA POINTER - LOW BYTE */
sfr DPH = 0x83; /* DATA POINTER - HIGH BYTE */
sfr P4 = 0x84; /* PORT 4 */
sfr P5 = 0x85; /* PORT 5 */
sfr P6 = 0x86; /* PORT 6 */
sfr PCON = 0x87; /* POWER CONTROL */
sfr TCON = 0x88; /* TIMER CONTROL */
sfr TMOD = 0x89; /* TIMER MODE */
sfr TL0 = 0x8A; /* TIMER 0 - LOW BYTE */
sfr TL1 = 0x8B; /* TIMER 1 - LOW BYTE */
sfr TH0 = 0x8C; /* TIMER 0 - HIGH BYTE */
sfr TH1 = 0x8D; /* TIMER 1 - HIGH BYTE */
sfr CKCON = 0x8E; /* CLOCK CONTROL */
sfr PSCTL = 0x8F; /* PROGRAM STORE R/W CONTROL */
sfr P1 = 0x90; /* PORT 1 */
sfr TMR3CN = 0x91; /* TIMER 3 CONTROL */
sfr TMR3RLL = 0x92; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
sfr TMR3RLH = 0x93; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
sfr TMR3L = 0x94; /* TIMER 3 - LOW BYTE */
sfr TMR3H = 0x95; /* TIMER 3 - HIGH BYTE */
sfr P7 = 0x96; /* PORT 7 */
sfr SCON0 = 0x98; /* SERIAL PORT 0 CONTROL */
sfr SBUF0 = 0x99; /* SERIAL PORT 0 BUFFER */
sfr SPI0CFG = 0x9A; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
sfr SPI0DAT = 0x9B; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
sfr ADC1 = 0x9C; /* ADC 1 DATA */
sfr SPI0CKR = 0x9D; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
sfr CPT0CN = 0x9E; /* COMPARATOR 0 CONTROL */
sfr CPT1CN = 0x9F; /* COMPARATOR 1 CONTROL */
sfr P2 = 0xA0; /* PORT 2 */
sfr EMI0TC = 0xA1; /* EMIF TIMING CONTROL */
sfr EMI0CF = 0xA3; /* EXTERNAL MEMORY INTERFACE (EMIF) CONFIGURATION */
sfr P0MDOUT = 0xA4; /* PORT 0 OUTPUT MODE CONFIGURATION */
sfr P1MDOUT = 0xA5; /* PORT 1 OUTPUT MODE CONFIGURATION */
sfr P2MDOUT = 0xA6; /* PORT 2 OUTPUT MODE CONFIGURATION */
sfr P3MDOUT = 0xA7; /* PORT 3 OUTPUT MODE CONFIGURATION */
sfr IE = 0xA8; /* INTERRUPT ENABLE */
sfr SADDR0 = 0xA9; /* SERIAL PORT 0 SLAVE ADDRESS */
sfr ADC1CN = 0xAA; /* ADC 1 CONTROL */
sfr ADC1CF = 0xAB; /* ADC 1 ANALOG MUX CONFIGURATION */
sfr AMX1SL = 0xAC; /* ADC 1 ANALOG MUX CHANNEL SELECT */
sfr P3IF = 0xAD; /* PORT 3 EXTERNAL INTERRUPT FLAGS */
sfr SADEN1 = 0xAE; /* SERIAL PORT 1 SLAVE ADDRESS MASK */
sfr EMI0CN = 0xAF; /* EXTERNAL MEMORY INTERFACE CONTROL */
sfr P3 = 0xB0; /* PORT 3 */
sfr OSCXCN = 0xB1; /* EXTERNAL OSCILLATOR CONTROL */
sfr OSCICN = 0xB2; /* INTERNAL OSCILLATOR CONTROL */
sfr P74OUT = 0xB5; /* PORTS 4 - 7 OUTPUT MODE */
sfr FLSCL = 0xB6; /* FLASH MEMORY TIMING PRESCALER */
sfr FLACL = 0xB7; /* FLASH ACESS LIMIT */
sfr IP = 0xB8; /* INTERRUPT PRIORITY */
sfr SADEN0 = 0xB9; /* SERIAL PORT 0 SLAVE ADDRESS MASK */
sfr AMX0CF = 0xBA; /* ADC 0 MUX CONFIGURATION */
sfr AMX0SL = 0xBB; /* ADC 0 MUX CHANNEL SELECTION */
sfr ADC0CF = 0xBC; /* ADC 0 CONFIGURATION */
sfr P1MDIN = 0xBD; /* PORT 1 INPUT MODE */
sfr ADC0L = 0xBE; /* ADC 0 DATA - LOW BYTE */
sfr ADC0H = 0xBF; /* ADC 0 DATA - HIGH BYTE */
sfr SMB0CN = 0xC0; /* SMBUS 0 CONTROL */
sfr SMB0STA = 0xC1; /* SMBUS 0 STATUS */
sfr SMB0DAT = 0xC2; /* SMBUS 0 DATA */
sfr SMB0ADR = 0xC3; /* SMBUS 0 SLAVE ADDRESS */
sfr ADC0GTL = 0xC4; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
sfr ADC0GTH = 0xC5; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
sfr ADC0LTL = 0xC6; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
sfr ADC0LTH = 0xC7; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
sfr T2CON = 0xC8; /* TIMER 2 CONTROL */
sfr T4CON = 0xC9; /* TIMER 4 CONTROL */
sfr RCAP2L = 0xCA; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
sfr RCAP2H = 0xCB; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
sfr TL2 = 0xCC; /* TIMER 2 - LOW BYTE */
sfr TH2 = 0 +1 108 ACC DATA 0E0H ; ACCUMULATOR
00E1 +1 109 XBR0 DATA 0E1H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 0
00E2 +1 110 XBR1 DATA 0E2H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 1
00E3 +1 111 XBR2 DATA 0E3H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 2
00E4 +1 112 RCAP4L DATA 0E4H ; TIMER 4 CAPTURE REGISTER - LOW BYTE
00E5 +1 113 RCAP4H DATA 0E5H ; TIMER 4 CAPTURE REGISTER - HIGH BYTE
00E6 +1 114 EIE1 DATA 0E6H ; EXTERNAL INTERRUPT ENABLE 1
00E7 +1 115 EIE2 DATA 0E7H ; EXTERNAL INTERRUPT ENABLE 2
00E8 +1 116 ADC0CN DATA 0E8H ; ADC 0 CONTROL
00E9 +1 117 PCA0L DATA 0E9H ; PCA 0 TIMER - LOW BYTE
00EA +1 118 PCA0CPL0 DATA 0EAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE
00EB +1 119 PCA0CPL1 DATA 0EBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE
00EC +1 120 PCA0CPL2 DATA 0ECH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE
00ED +1 121 PCA0CPL3 DATA 0EDH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE
00EE +1 122 PCA0CPL4 DATA 0EEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE
00EF +1 123 RSTSRC DATA 0EFH ; RESET SOURCE
A51 MACRO ASSEMBLER ISD4004PLAY 11/08/2005 16:12:09 PAGE 3
00F0 +1 124 B DATA 0F0H ; B REGISTER
00F1 +1 125 SCON1 DATA 0F1H ; SERIAL PORT 1 CONTROL
00F2 +1 126 SBUF1 DATA 0F2H ; SERAIL PORT 1 DATA
00F3 +1 127 SADDR1 DATA 0F3H ; SERAIL PORT 1
00F4 +1 128 TL4 DATA 0F4H ; TIMER 4 DATA - LOW BYTE
00F5 +1 129 TH4 DATA 0F5H ; TIMER 4 DATA - HIGH BYTE
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