;-----------------------------------------------------------------------------;	Copyright (C) 2001 CYGNAL INTEGRATED PRODUCTS, INC.; 	All rights reserved.;;; 	FILE NAME  	: C8051F020.INC ; 	TARGET MCUs	: C8051F020, 'F021, 'F022, 'F023 ; 	DESCRIPTION	: Register/bit definitions for the C8051F02x product family.  ;; 	REVISION 1.0 	;;-----------------------------------------------------------------------------;REGISTER DEFINITIONS;P0       DATA  080H   ; PORT 0SP       DATA  081H   ; STACK POINTERDPL      DATA  082H   ; DATA POINTER - LOW BYTEDPH      DATA  083H   ; DATA POINTER - HIGH BYTEP4       DATA  084H   ; PORT 4P5       DATA  085H   ; PORT 5P6       DATA  086H   ; PORT 6PCON     DATA  087H   ; POWER CONTROLTCON     DATA  088H   ; TIMER CONTROLTMOD     DATA  089H   ; TIMER MODETL0      DATA  08AH   ; TIMER 0 - LOW BYTETL1      DATA  08BH   ; TIMER 1 - LOW BYTETH0      DATA  08CH   ; TIMER 0 - HIGH BYTETH1      DATA  08DH   ; TIMER 1 - HIGH BYTECKCON    DATA  08EH   ; CLOCK CONTROLPSCTL    DATA  08FH   ; PROGRAM STORE R/W CONTROLP1       DATA  090H   ; PORT 1TMR3CN   DATA  091H   ; TIMER 3 CONTROLTMR3RLL  DATA  092H   ; TIMER 3 RELOAD REGISTER - LOW BYTETMR3RLH  DATA  093H   ; TIMER 3 RELOAD REGISTER - HIGH BYTETMR3L    DATA  094H   ; TIMER 3 - LOW BYTETMR3H    DATA  095H   ; TIMER 3 - HIGH BYTEP7       DATA  096H   ; PORT 7SCON0    DATA  098H   ; SERIAL PORT 0 CONTROLSBUF0    DATA  099H   ; SERIAL PORT 0 BUFFERSPI0CFG  DATA  09AH   ; SERIAL PERIPHERAL INTERFACE 0 CONFIGURATIONSPI0DAT  DATA  09BH   ; SERIAL PERIPHERAL INTERFACE 0 DATAADC1     DATA  09CH   ; ADC 1 DATASPI0CKR  DATA  09DH   ; SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROLCPT0CN   DATA  09EH   ; COMPARATOR 0 CONTROLCPT1CN   DATA  09FH   ; COMPARATOR 1 CONTROL P2       DATA  0A0H   ; PORT 2EMI0TC   DATA  0A1H   ; EMIF TIMING CONTROLEMI0CF   DATA  0A3H   ; EXTERNAL MEMORY INTERFACE (EMIF) CONFIGURATIONP0MDOUT  DATA  0A4H   ; PORT 0 OUTPUT MODE CONFIGURATIONP1MDOUT  DATA  0A5H   ; PORT 1 OUTPUT MODE CONFIGURATIONP2MDOUT  DATA  0A6H   ; PORT 2 OUTPUT MODE CONFIGURATIONP3MDOUT  DATA  0A7H   ; PORT 3 OUTPUT MODE CONFIGURATIONIE       DATA  0A8H   ; INTERRUPT ENABLESADDR0   DATA  0A9H   ; SERIAL PORT 0 SLAVE ADDRESSADC1CN	DATA  0AAH   ; ADC 1 CONTROLADC1CF   DATA  0ABH   ; ADC 1 ANALOG MUX CONFIGURATIONAMX1SL   DATA  0ACH   ; ADC 1 ANALOG MUX CHANNEL SELECTP3IF     DATA  0ADH   ; PORT 3 EXTERNAL INTERRUPT FLAGSSADEN1   DATA  0AEH   ; SERIAL PORT 1 SLAVE ADDRESS MASKEMI0CN   DATA  0AFH   ; EXTERNAL MEMORY INTERFACE CONTROLP3       DATA  0B0H   ; PORT 3OSCXCN   DATA  0B1H   ; EXTERNAL OSCILLATOR CONTROLOSCICN   DATA  0B2H   ; INTERNAL OSCILLATOR CONTROLP74OUT   DATA  0B5H   ; PORTS 4 - 7 OUTPUT MODEFLSCL    DATA  0B6H   ; FLASH MEMORY TIMING PRESCALERFLACL    DATA  0B7H   ; FLASH ACESS LIMIT IP       DATA  0B8H   ; INTERRUPT PRIORITYSADEN0   DATA  0B9H   ; SERIAL PORT 0 SLAVE ADDRESS MASKAMX0CF   DATA  0BAH   ; ADC 0 MUX CONFIGURATIONAMX0SL   DATA  0BBH   ; ADC 0 MUX CHANNEL SELECTIONADC0CF   DATA  0BCH   ; ADC 0 CONFIGURATIONP1MDIN   DATA  0BDH   ; PORT 1 INPUT MODEADC0L    DATA  0BEH   ; ADC 0 DATA - LOW BYTEADC0H    DATA  0BFH   ; ADC 0 DATA - HIGH BYTE SMB0CN   DATA  0C0H   ; SMBUS 0 CONTROLSMB0STA  DATA  0C1H   ; SMBUS 0 STATUSSMB0DAT  DATA  0C2H   ; SMBUS 0 DATA SMB0ADR  DATA  0C3H   ; SMBUS 0 SLAVE ADDRESSADC0GTL  DATA  0C4H   ; ADC 0 GREATER-THAN REGISTER - LOW BYTEADC0GTH  DATA  0C5H   ; ADC 0 GREATER-THAN REGISTER - HIGH BYTEADC0LTL  DATA  0C6H   ; ADC 0 LESS-THAN REGISTER - LOW BYTEADC0LTH  DATA  0C7H   ; ADC 0 LESS-THAN REGISTER - HIGH BYTET2CON    DATA  0C8H   ; TIMER 2 CONTROLT4CON    DATA  0C9H   ; TIMER 4 CONTROLRCAP2L   DATA  0CAH   ; TIMER 2 CAPTURE REGISTER - LOW BYTERCAP2H   DATA  0CBH   ; TIMER 2 CAPTURE REGISTER - HIGH BYTETL2      DATA  0CCH   ; TIMER 2 - LOW BYTETH2      DATA  0CDH   ; TIMER 2 - HIGH BYTESMB0CR   DATA  0CFH   ; SMBUS 0 CLOCK RATEPSW      DATA  0D0H   ; PROGRAM STATUS WORDREF0CN   DATA  0D1H   ; VOLTAGE REFERENCE 0 CONTROLDAC0L    DATA  0D2H   ; DAC 0 REGISTER - LOW BYTEDAC0H    DATA  0D3H   ; DAC 0 REGISTER - HIGH BYTEDAC0CN   DATA  0D4H   ; DAC 0 CONTROLDAC1L    DATA  0D5H   ; DAC 1 REGISTER - LOW BYTEDAC1H    DATA  0D6H   ; DAC 1 REGISTER - HIGH BYTEDAC1CN   DATA  0D7H   ; DAC 1 CONTROLPCA0CN   DATA  0D8H   ; PCA 0 COUNTER CONTROLPCA0MD   DATA  0D9H   ; PCA 0 COUNTER MODEPCA0CPM0 DATA  0DAH   ; CONTROL REGISTER FOR PCA 0 MODULE 0PCA0CPM1 DATA  0DBH   ; CONTROL REGISTER FOR PCA 0 MODULE 1PCA0CPM2 DATA  0DCH   ; CONTROL REGISTER FOR PCA 0 MODULE 2PCA0CPM3 DATA  0DDH   ; CONTROL REGISTER FOR PCA 0 MODULE 3PCA0CPM4 DATA  0DEH   ; CONTROL REGISTER FOR PCA 0 MODULE 4ACC      DATA  0E0H   ; ACCUMULATORXBR0     DATA  0E1H   ; DIGITAL CROSSBAR CONFIGURATION REGISTER 0XBR1     DATA  0E2H   ; DIGITAL CROSSBAR CONFIGURATION REGISTER 1XBR2     DATA  0E3H   ; DIGITAL CROSSBAR CONFIGURATION REGISTER 2RCAP4L   DATA  0E4H   ; TIMER 4 CAPTURE REGISTER - LOW BYTERCAP4H   DATA  0E5H   ; TIMER 4 CAPTURE REGISTER - HIGH BYTEEIE1     DATA  0E6H   ; EXTERNAL INTERRUPT ENABLE 1EIE2     DATA  0E7H   ; EXTERNAL INTERRUPT ENABLE 2ADC0CN   DATA  0E8H   ; ADC 0 CONTROLPCA0L    DATA  0E9H   ; PCA 0 TIMER - LOW BYTEPCA0CPL0 DATA  0EAH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTEPCA0CPL1 DATA  0EBH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTEPCA0CPL2 DATA  0ECH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTEPCA0CPL3 DATA  0EDH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTEPCA0CPL4 DATA  0EEH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTERSTSRC   DATA  0EFH   ; RESET SOURCE B        DATA  0F0H   ; B REGISTERSCON1    DATA  0F1H   ; SERIAL PORT 1 CONTROLSBUF1    DATA  0F2H   ; SERAIL PORT 1 DATASADDR1   DATA  0F3H   ; SERAIL PORT 1 TL4      DATA  0F4H   ; TIMER 4 DATA - LOW BYTETH4      DATA  0F5H   ; TIMER 4 DATA - HIGH BYTEEIP1     DATA  0F6H   ; EXTERNAL INTERRUPT PRIORITY REGISTER 1EIP2     DATA  0F7H   ; EXTERNAL INTERRUPT PRIORITY REGISTER 2SPI0CN   DATA  0F8H   ; SERIAL PERIPHERAL INTERFACE 0 CONTROL PCA0H    DATA  0F9H   ; PCA 0 TIMER - HIGH BYTEPCA0CPH0 DATA  0FAH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTEPCA0CPH1 DATA  0FBH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTEPCA0CPH2 DATA  0FCH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTEPCA0CPH3 DATA  0FDH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTEPCA0CPH4 DATA  0FEH   ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTEWDTCN    DATA  0FFH   ; WATCHDOG TIMER CONTROL ;;------------------------------------------------------------------------------;BIT DEFINITIONS;; TCON 88HIT0      BIT   TCON.0 ; EXT. INTERRUPT 0 TYPEIE0      BIT   TCON.1 ; EXT. INTERRUPT 0 EDGE FLAGIT1      BIT   TCON.2 ; EXT. INTERRUPT 1 TYPEIE1      BIT   TCON.3 ; EXT. INTERRUPT 1 EDGE FLAGTR0      BIT   TCON.4 ; TIMER 0 ON/OFF CONTROLTF0      BIT   TCON.5 ; TIMER 0 OVERFLOW FLAGTR1      BIT   TCON.6 ; TIMER 1 ON/OFF CONTROLTF1      BIT   TCON.7 ; TIMER 1 OVERFLOW FLAG;; SCON0 98HRI       BIT   SCON0.0 ; RECEIVE INTERRUPT FLAGTI       BIT   SCON0.1 ; TRANSMIT INTERRUPT FLAGRB8      BIT   SCON0.2 ; RECEIVE BIT 8TB8      BIT   SCON0.3 ; TRANSMIT BIT 8REN      BIT   SCON0.4 ; RECEIVE ENABLESM2      BIT   SCON0.5 ; MULTIPROCESSOR COMMUNICATION ENABLESM1      BIT   SCON0.6 ; SERIAL MODE CONTROL BIT 1SM0      BIT   SCON0.7 ; SERIAL MODE CONTROL BIT 0; ; IE A8HEX0      BIT   IE.0   ; EXTERNAL INTERRUPT 0 ENABLEET0      BIT   IE.1   ; TIMER 0 INTERRUPT ENABLEEX1      BIT   IE.2   ; EXTERNAL INTERRUPT 1 ENABLEET1      BIT   IE.3   ; TIMER 1 INTERRUPT ENABLEES       BIT   IE.4   ; SERIAL PORT INTERRUPT ENABLEET2      BIT   IE.5   ; TIMER 2 INTERRUPT ENABLEEA       BIT   IE.7   ; GLOBAL INTERRUPT ENABLE;; IP B8HPX0      BIT   IP.0   ; EXTERNAL INTERRUPT 0 PRIORITYPT0      BIT   IP.1   ; TIMER 0 PRIORITYPX1      BIT   IP.2   ; EXTERNAL INTERRUPT 1 PRIORITYPT1      BIT   IP.3   ; TIMER 1 PRIORITYPS       BIT   IP.4   ; SERIAL PORT PRIORITYPT2      BIT   IP.5   ; TIMER 2 PRIORITY;; SMB0CN C0HSMBTOE   BIT   SMB0CN.0 ; SMBUS 0 TIMEOUT ENABLESMBFTE   BIT   SMB0CN.1 ; SMBUS 0 FREE TIMER ENABLEAA       BIT   SMB0CN.2 ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAGSI       BIT   SMB0CN.3 ; SMBUS 0 INTERRUPT PENDING FLAGSTO      BIT   SMB0CN.4 ; SMBUS 0 STOP FLAGSTA      BIT   SMB0CN.5 ; SMBUS 0 START FLAGENSMB    BIT   SMB0CN.6 ; SMBUS 0 ENABLE ;; T2CON C8HCPRL2    BIT   T2CON.0 ; CAPTURE OR RELOAD SELECTCT2      BIT   T2CON.1 ; TIMER OR COUNTER SELECTTR2      BIT   T2CON.2 ; TIMER 2 ON/OFF CONTROLEXEN2    BIT   T2CON.3 ; TIMER 2 EXTERNAL ENABLE FLAGTCLK     BIT   T2CON.4 ; TRANSMIT CLOCK FLAGRCLK     BIT   T2CON.5 ; RECEIVE CLOCK FLAGEXF2     BIT   T2CON.6 ; EXTERNAL FLAGTF2      BIT   T2CON.7 ; TIMER 2 OVERFLOW FLAG;; PSW D0HP        BIT   PSW.0  ; ACCUMULATOR PARITY FLAGF1       BIT   PSW.1  ; USER FLAG 1OV       BIT   PSW.2  ; OVERFLOW FLAGRS0      BIT   PSW.3  ; REGISTER BANK SELECT 0RS1      BIT   PSW.4  ; REGISTER BANK SELECT 1F0       BIT   PSW.5  ; USER FLAG 0AC       BIT   PSW.6  ; AUXILIARY CARRY FLAGCY       BIT   PSW.7  ; CARRY FLAG;; PCA0CN D8HCCF0     BIT   PCA0CN.0 ; PCA 0 MODULE 0 INTERRUPT FLAGCCF1     BIT   PCA0CN.1 ; PCA 0 MODULE 1 INTERRUPT FLAGCCF2     BIT   PCA0CN.2 ; PCA 0 MODULE 2 INTERRUPT FLAGCCF3     BIT   PCA0CN.3 ; PCA 0 MODULE 3 INTERRUPT FLAGCCF4     BIT   PCA0CN.4 ; PCA 0 MODULE 4 INTERRUPT FLAGCR       BIT   PCA0CN.6 ; PCA 0 COUNTER RUN CONTROL BITCF       BIT   PCA0CN.7 ; PCA 0 COUNTER OVERFLOW FLAG;; ADC0CN E8HAD0LJST  BIT   ADC0CN.0 ; ADC 0 RIGHT JUSTIFY DATA BITAD0WINT  BIT   ADC0CN.1 ; ADC 0 WINDOW COMPARE INTERRUPT FLAGAD0STM0  BIT   ADC0CN.2 ; ADC 0 START OF CONVERSION MODE BIT 0AD0STM1  BIT   ADC0CN.3 ; ADC 0 START OF CONVERSION MODE BIT 1AD0BUSY  BIT   ADC0CN.4 ; ADC 0 BUSY FLAGAD0INT   BIT   ADC0CN.5 ; ADC 0 CONVERISION COMPLETE INTERRUPT FLAG AD0TM    BIT   ADC0CN.6 ; ADC 0 TRACK MODEAD0EN    BIT   ADC0CN.7 ; ADC 0 ENABLE;; SPI0CN F8HSPIEN    BIT   SPI0CN.0 ; SPI 0 SPI ENABLEMSTEN    BIT   SPI0CN.1 ; SPI 0 MASTER ENABLESLVSEL   BIT   SPI0CN.2 ; SPI 0 SLAVE SELECTTXBSY    BIT   SPI0CN.3 ; SPI 0 TX BUSY FLAGRXOVRN   BIT   SPI0CN.4 ; SPI 0 RX OVERRUN FLAGMODF     BIT   SPI0CN.5 ; SPI 0 MODE FAULT FLAGWCOL     BIT   SPI0CN.6 ; SPI 0 WRITE COLLISION FLAGSPIF     BIT   SPI0CN.7 ; SPI 0 INTERRUPT FLAG