?? wonoffp4.lst
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A51 MACRO ASSEMBLER WONOFFP4 02/10/2006 20:20:32 PAGE 1
MACRO ASSEMBLER A51 V7.04a
OBJECT MODULE PLACED IN WONOFFP4.OBJ
ASSEMBLER INVOKED BY: C:\SiLabs\MCU\IDEfiles\C51\BIN\a51.exe WONOFFP4.ASM XR GEN DB EP NOMOD51
LOC OBJ LINE SOURCE
1 ;參考程序A : WONOFFP4.ASM 8個LED燈依次循環點亮.
2 ;$include (c8051f020.inc)
+1 3 ;-----------------------------------------------------------------------------
+1 4 ; Copyright (C) 2001 CYGNAL INTEGRATED PRODUCTS, INC.
+1 5 ; All rights reserved.
+1 6 ;
+1 7 ;
+1 8 ; FILE NAME : C8051F020.INC
+1 9 ; TARGET MCUs : C8051F020, 'F021, 'F022, 'F023
+1 10 ; DESCRIPTION : Register/bit definitions for the C8051F02x product family.
+1 11 ;
+1 12 ; REVISION 1.0
+1 13 ;
+1 14 ;-----------------------------------------------------------------------------
+1 15 ;REGISTER DEFINITIONS
+1 16 ;
0080 +1 17 P0 DATA 080H ; PORT 0
0081 +1 18 SP DATA 081H ; STACK POINTER
0082 +1 19 DPL DATA 082H ; DATA POINTER - LOW BYTE
0083 +1 20 DPH DATA 083H ; DATA POINTER - HIGH BYTE
0084 +1 21 P4 DATA 084H ; PORT 4
0085 +1 22 P5 DATA 085H ; PORT 5
0086 +1 23 P6 DATA 086H ; PORT 6
0087 +1 24 PCON DATA 087H ; POWER CONTROL
0088 +1 25 TCON DATA 088H ; TIMER CONTROL
0089 +1 26 TMOD DATA 089H ; TIMER MODE
008A +1 27 TL0 DATA 08AH ; TIMER 0 - LOW BYTE
008B +1 28 TL1 DATA 08BH ; TIMER 1 - LOW BYTE
008C +1 29 TH0 DATA 08CH ; TIMER 0 - HIGH BYTE
008D +1 30 TH1 DATA 08DH ; TIMER 1 - HIGH BYTE
008E +1 31 CKCON DATA 08EH ; CLOCK CONTROL
008F +1 32 PSCTL DATA 08FH ; PROGRAM STORE R/W CONTROL
0090 +1 33 P1 DATA 090H ; PORT 1
0091 +1 34 TMR3CN DATA 091H ; TIMER 3 CONTROL
0092 +1 35 TMR3RLL DATA 092H ; TIMER 3 RELOAD REGISTER - LOW BYTE
0093 +1 36 TMR3RLH DATA 093H ; TIMER 3 RELOAD REGISTER - HIGH BYTE
0094 +1 37 TMR3L DATA 094H ; TIMER 3 - LOW BYTE
0095 +1 38 TMR3H DATA 095H ; TIMER 3 - HIGH BYTE
0096 +1 39 P7 DATA 096H ; PORT 7
0098 +1 40 SCON0 DATA 098H ; SERIAL PORT 0 CONTROL
0099 +1 41 SBUF0 DATA 099H ; SERIAL PORT 0 BUFFER
009A +1 42 SPI0CFG DATA 09AH ; SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION
009B +1 43 SPI0DAT DATA 09BH ; SERIAL PERIPHERAL INTERFACE 0 DATA
009C +1 44 ADC1 DATA 09CH ; ADC 1 DATA
009D +1 45 SPI0CKR DATA 09DH ; SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL
009E +1 46 CPT0CN DATA 09EH ; COMPARATOR 0 CONTROL
009F +1 47 CPT1CN DATA 09FH ; COMPARATOR 1 CONTROL
00A0 +1 48 P2 DATA 0A0H ; PORT 2
00A1 +1 49 EMI0TC DATA 0A1H ; EMIF TIMING CONTROL
00A3 +1 50 EMI0CF DATA 0A3H ; EXTERNAL MEMORY INTERFACE (EMIF) CONFIGURATION
00A4 +1 51 P0MDOUT DATA 0A4H ; PORT 0 OUTPUT MODE CONFIGURATION
00A5 +1 52 P1MDOUT DATA 0A5H ; PORT 1 OUTPUT MODE CONFIGURATION
00A6 +1 53 P2MDOUT DATA 0A6H ; PORT 2 OUTPUT MODE CONFIGURATION
00A7 +1 54 P3MDOUT DATA 0A7H ; PORT 3 OUTPUT MODE CONFIGURATION
00A8 +1 55 IE DATA 0A8H ; INTERRUPT ENABLE
00A9 +1 56 SADDR0 DATA 0A9H ; SERIAL PORT 0 SLAVE ADDRESS
00AA +1 57 ADC1CN DATA 0AAH ; ADC 1 CONTROL
00AB +1 58 ADC1CF DATA 0ABH ; ADC 1 ANALOG MUX CONFIGURATION
A51 MACRO ASSEMBLER WONOFFP4 02/10/2006 20:20:32 PAGE 2
00AC +1 59 AMX1SL DATA 0ACH ; ADC 1 ANALOG MUX CHANNEL SELECT
00AD +1 60 P3IF DATA 0ADH ; PORT 3 EXTERNAL INTERRUPT FLAGS
00AE +1 61 SADEN1 DATA 0AEH ; SERIAL PORT 1 SLAVE ADDRESS MASK
00AF +1 62 EMI0CN DATA 0AFH ; EXTERNAL MEMORY INTERFACE CONTROL
00B0 +1 63 P3 DATA 0B0H ; PORT 3
00B1 +1 64 OSCXCN DATA 0B1H ; EXTERNAL OSCILLATOR CONTROL
00B2 +1 65 OSCICN DATA 0B2H ; INTERNAL OSCILLATOR CONTROL
00B5 +1 66 P74OUT DATA 0B5H ; PORTS 4 - 7 OUTPUT MODE
00B6 +1 67 FLSCL DATA 0B6H ; FLASH MEMORY TIMING PRESCALER
00B7 +1 68 FLACL DATA 0B7H ; FLASH ACESS LIMIT
00B8 +1 69 IP DATA 0B8H ; INTERRUPT PRIORITY
00B9 +1 70 SADEN0 DATA 0B9H ; SERIAL PORT 0 SLAVE ADDRESS MASK
00BA +1 71 AMX0CF DATA 0BAH ; ADC 0 MUX CONFIGURATION
00BB +1 72 AMX0SL DATA 0BBH ; ADC 0 MUX CHANNEL SELECTION
00BC +1 73 ADC0CF DATA 0BCH ; ADC 0 CONFIGURATION
00BD +1 74 P1MDIN DATA 0BDH ; PORT 1 INPUT MODE
00BE +1 75 ADC0L DATA 0BEH ; ADC 0 DATA - LOW BYTE
00BF +1 76 ADC0H DATA 0BFH ; ADC 0 DATA - HIGH BYTE
00C0 +1 77 SMB0CN DATA 0C0H ; SMBUS 0 CONTROL
00C1 +1 78 SMB0STA DATA 0C1H ; SMBUS 0 STATUS
00C2 +1 79 SMB0DAT DATA 0C2H ; SMBUS 0 DATA
00C3 +1 80 SMB0ADR DATA 0C3H ; SMBUS 0 SLAVE ADDRESS
00C4 +1 81 ADC0GTL DATA 0C4H ; ADC 0 GREATER-THAN REGISTER - LOW BYTE
00C5 +1 82 ADC0GTH DATA 0C5H ; ADC 0 GREATER-THAN REGISTER - HIGH BYTE
00C6 +1 83 ADC0LTL DATA 0C6H ; ADC 0 LESS-THAN REGISTER - LOW BYTE
00C7 +1 84 ADC0LTH DATA 0C7H ; ADC 0 LESS-THAN REGISTER - HIGH BYTE
00C8 +1 85 T2CON DATA 0C8H ; TIMER 2 CONTROL
00C9 +1 86 T4CON DATA 0C9H ; TIMER 4 CONTROL
00CA +1 87 RCAP2L DATA 0CAH ; TIMER 2 CAPTURE REGISTER - LOW BYTE
00CB +1 88 RCAP2H DATA 0CBH ; TIMER 2 CAPTURE REGISTER - HIGH BYTE
00CC +1 89 TL2 DATA 0CCH ; TIMER 2 - LOW BYTE
00CD +1 90 TH2 DATA 0CDH ; TIMER 2 - HIGH BYTE
00CF +1 91 SMB0CR DATA 0CFH ; SMBUS 0 CLOCK RATE
00D0 +1 92 PSW DATA 0D0H ; PROGRAM STATUS WORD
00D1 +1 93 REF0CN DATA 0D1H ; VOLTAGE REFERENCE 0 CONTROL
00D2 +1 94 DAC0L DATA 0D2H ; DAC 0 REGISTER - LOW BYTE
00D3 +1 95 DAC0H DATA 0D3H ; DAC 0 REGISTER - HIGH BYTE
00D4 +1 96 DAC0CN DATA 0D4H ; DAC 0 CONTROL
00D5 +1 97 DAC1L DATA 0D5H ; DAC 1 REGISTER - LOW BYTE
00D6 +1 98 DAC1H DATA 0D6H ; DAC 1 REGISTER - HIGH BYTE
00D7 +1 99 DAC1CN DATA 0D7H ; DAC 1 CONTROL
00D8 +1 100 PCA0CN DATA 0D8H ; PCA 0 COUNTER CONTROL
00D9 +1 101 PCA0MD DATA 0D9H ; PCA 0 COUNTER MODE
00DA +1 102 PCA0CPM0 DATA 0DAH ; CONTROL REGISTER FOR PCA 0 MODULE 0
00DB +1 103 PCA0CPM1 DATA 0DBH ; CONTROL REGISTER FOR PCA 0 MODULE 1
00DC +1 104 PCA0CPM2 DATA 0DCH ; CONTROL REGISTER FOR PCA 0 MODULE 2
00DD +1 105 PCA0CPM3 DATA 0DDH ; CONTROL REGISTER FOR PCA 0 MODULE 3
00DE +1 106 PCA0CPM4 DATA 0DEH ; CONTROL REGISTER FOR PCA 0 MODULE 4
00E0 +1 107 ACC DATA 0E0H ; ACCUMULATOR
00E1 +1 108 XBR0 DATA 0E1H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 0
00E2 +1 109 XBR1 DATA 0E2H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 1
00E3 +1 110 XBR2 DATA 0E3H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 2
00E4 +1 111 RCAP4L DATA 0E4H ; TIMER 4 CAPTURE REGISTER - LOW BYTE
00E5 +1 112 RCAP4H DATA 0E5H ; TIMER 4 CAPTURE REGISTER - HIGH BYTE
00E6 +1 113 EIE1 DATA 0E6H ; EXTERNAL INTERRUPT ENABLE 1
00E7 +1 114 EIE2 DATA 0E7H ; EXTERNAL INTERRUPT ENABLE 2
00E8 +1 115 ADC0CN DATA 0E8H ; ADC 0 CONTROL
00E9 +1 116 PCA0L DATA 0E9H ; PCA 0 TIMER - LOW BYTE
00EA +1 117 PCA0CPL0 DATA 0EAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE
00EB +1 118 PCA0CPL1 DATA 0EBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE
00EC +1 119 PCA0CPL2 DATA 0ECH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE
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