?? uart0rf.lst
字號:
00EE +1 121 PCA0CPL4 DATA 0EEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE
00EF +1 122 RSTSRC DATA 0EFH ; RESET SOURCE
00F0 +1 123 B DATA 0F0H ; B REGISTER
00F1 +1 124 SCON1 DATA 0F1H ; SERIAL PORT 1 CONTROL
A51 MACRO ASSEMBLER UART0RF 02/14/2006 08:38:19 PAGE 3
00F2 +1 125 SBUF1 DATA 0F2H ; SERAIL PORT 1 DATA
00F3 +1 126 SADDR1 DATA 0F3H ; SERAIL PORT 1
00F4 +1 127 TL4 DATA 0F4H ; TIMER 4 DATA - LOW BYTE
00F5 +1 128 TH4 DATA 0F5H ; TIMER 4 DATA - HIGH BYTE
00F6 +1 129 EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY REGISTER 1
00F7 +1 130 EIP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY REGISTER 2
00F8 +1 131 SPI0CN DATA 0F8H ; SERIAL PERIPHERAL INTERFACE 0 CONTROL
00F9 +1 132 PCA0H DATA 0F9H ; PCA 0 TIMER - HIGH BYTE
00FA +1 133 PCA0CPH0 DATA 0FAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE
00FB +1 134 PCA0CPH1 DATA 0FBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE
00FC +1 135 PCA0CPH2 DATA 0FCH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE
00FD +1 136 PCA0CPH3 DATA 0FDH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE
00FE +1 137 PCA0CPH4 DATA 0FEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE
00FF +1 138 WDTCN DATA 0FFH ; WATCHDOG TIMER CONTROL
+1 139 ;
+1 140 ;------------------------------------------------------------------------------
+1 141 ;BIT DEFINITIONS
+1 142 ;
+1 143 ; TCON 88H
0088 +1 144 IT0 BIT TCON.0 ; EXT. INTERRUPT 0 TYPE
0089 +1 145 IE0 BIT TCON.1 ; EXT. INTERRUPT 0 EDGE FLAG
008A +1 146 IT1 BIT TCON.2 ; EXT. INTERRUPT 1 TYPE
008B +1 147 IE1 BIT TCON.3 ; EXT. INTERRUPT 1 EDGE FLAG
008C +1 148 TR0 BIT TCON.4 ; TIMER 0 ON/OFF CONTROL
008D +1 149 TF0 BIT TCON.5 ; TIMER 0 OVERFLOW FLAG
008E +1 150 TR1 BIT TCON.6 ; TIMER 1 ON/OFF CONTROL
008F +1 151 TF1 BIT TCON.7 ; TIMER 1 OVERFLOW FLAG
+1 152 ;
+1 153 ; SCON0 98H
0098 +1 154 RI BIT SCON0.0 ; RECEIVE INTERRUPT FLAG
0099 +1 155 TI BIT SCON0.1 ; TRANSMIT INTERRUPT FLAG
009A +1 156 RB8 BIT SCON0.2 ; RECEIVE BIT 8
009B +1 157 TB8 BIT SCON0.3 ; TRANSMIT BIT 8
009C +1 158 REN BIT SCON0.4 ; RECEIVE ENABLE
009D +1 159 SM2 BIT SCON0.5 ; MULTIPROCESSOR COMMUNICATION ENABLE
009E +1 160 SM1 BIT SCON0.6 ; SERIAL MODE CONTROL BIT 1
009F +1 161 SM0 BIT SCON0.7 ; SERIAL MODE CONTROL BIT 0
+1 162 ;
+1 163 ; IE A8H
00A8 +1 164 EX0 BIT IE.0 ; EXTERNAL INTERRUPT 0 ENABLE
00A9 +1 165 ET0 BIT IE.1 ; TIMER 0 INTERRUPT ENABLE
00AA +1 166 EX1 BIT IE.2 ; EXTERNAL INTERRUPT 1 ENABLE
00AB +1 167 ET1 BIT IE.3 ; TIMER 1 INTERRUPT ENABLE
00AC +1 168 ES BIT IE.4 ; SERIAL PORT INTERRUPT ENABLE
00AD +1 169 ET2 BIT IE.5 ; TIMER 2 INTERRUPT ENABLE
00AF +1 170 EA BIT IE.7 ; GLOBAL INTERRUPT ENABLE
+1 171 ;
+1 172 ; IP B8H
00B8 +1 173 PX0 BIT IP.0 ; EXTERNAL INTERRUPT 0 PRIORITY
00B9 +1 174 PT0 BIT IP.1 ; TIMER 0 PRIORITY
00BA +1 175 PX1 BIT IP.2 ; EXTERNAL INTERRUPT 1 PRIORITY
00BB +1 176 PT1 BIT IP.3 ; TIMER 1 PRIORITY
00BC +1 177 PS BIT IP.4 ; SERIAL PORT PRIORITY
00BD +1 178 PT2 BIT IP.5 ; TIMER 2 PRIORITY
+1 179 ;
+1 180 ; SMB0CN C0H
00C0 +1 181 SMBTOE BIT SMB0CN.0 ; SMBUS 0 TIMEOUT ENABLE
00C1 +1 182 SMBFTE BIT SMB0CN.1 ; SMBUS 0 FREE TIMER ENABLE
00C2 +1 183 AA BIT SMB0CN.2 ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG
00C3 +1 184 SI BIT SMB0CN.3 ; SMBUS 0 INTERRUPT PENDING FLAG
00C4 +1 185 STO BIT SMB0CN.4 ; SMBUS 0 STOP FLAG
00C5 +1 186 STA BIT SMB0CN.5 ; SMBUS 0 START FLAG
00C6 +1 187 ENSMB BIT SMB0CN.6 ; SMBUS 0 ENABLE
+1 188 ;
+1 189 ; T2CON C8H
00C8 +1 190 CPRL2 BIT T2CON.0 ; CAPTURE OR RELOAD SELECT
A51 MACRO ASSEMBLER UART0RF 02/14/2006 08:38:19 PAGE 4
00C9 +1 191 CT2 BIT T2CON.1 ; TIMER OR COUNTER SELECT
00CA +1 192 TR2 BIT T2CON.2 ; TIMER 2 ON/OFF CONTROL
00CB +1 193 EXEN2 BIT T2CON.3 ; TIMER 2 EXTERNAL ENABLE FLAG
00CC +1 194 TCLK BIT T2CON.4 ; TRANSMIT CLOCK FLAG
00CD +1 195 RCLK BIT T2CON.5 ; RECEIVE CLOCK FLAG
00CE +1 196 EXF2 BIT T2CON.6 ; EXTERNAL FLAG
00CF +1 197 TF2 BIT T2CON.7 ; TIMER 2 OVERFLOW FLAG
+1 198 ;
+1 199 ; PSW D0H
00D0 +1 200 P BIT PSW.0 ; ACCUMULATOR PARITY FLAG
00D1 +1 201 F1 BIT PSW.1 ; USER FLAG 1
00D2 +1 202 OV BIT PSW.2 ; OVERFLOW FLAG
00D3 +1 203 RS0 BIT PSW.3 ; REGISTER BANK SELECT 0
00D4 +1 204 RS1 BIT PSW.4 ; REGISTER BANK SELECT 1
00D5 +1 205 F0 BIT PSW.5 ; USER FLAG 0
00D6 +1 206 AC BIT PSW.6 ; AUXILIARY CARRY FLAG
00D7 +1 207 CY BIT PSW.7 ; CARRY FLAG
+1 208 ;
+1 209 ; PCA0CN D8H
00D8 +1 210 CCF0 BIT PCA0CN.0 ; PCA 0 MODULE 0 INTERRUPT FLAG
00D9 +1 211 CCF1 BIT PCA0CN.1 ; PCA 0 MODULE 1 INTERRUPT FLAG
00DA +1 212 CCF2 BIT PCA0CN.2 ; PCA 0 MODULE 2 INTERRUPT FLAG
00DB +1 213 CCF3 BIT PCA0CN.3 ; PCA 0 MODULE 3 INTERRUPT FLAG
00DC +1 214 CCF4 BIT PCA0CN.4 ; PCA 0 MODULE 4 INTERRUPT FLAG
00DE +1 215 CR BIT PCA0CN.6 ; PCA 0 COUNTER RUN CONTROL BIT
00DF +1 216 CF BIT PCA0CN.7 ; PCA 0 COUNTER OVERFLOW FLAG
+1 217 ;
+1 218 ; ADC0CN E8H
00E8 +1 219 AD0LJST BIT ADC0CN.0 ; ADC 0 RIGHT JUSTIFY DATA BIT
00E9 +1 220 AD0WINT BIT ADC0CN.1 ; ADC 0 WINDOW COMPARE INTERRUPT FLAG
00EA +1 221 AD0STM0 BIT ADC0CN.2 ; ADC 0 START OF CONVERSION MODE BIT 0
00EB +1 222 AD0STM1 BIT ADC0CN.3 ; ADC 0 START OF CONVERSION MODE BIT 1
00EC +1 223 AD0BUSY BIT ADC0CN.4 ; ADC 0 BUSY FLAG
00ED +1 224 AD0INT BIT ADC0CN.5 ; ADC 0 CONVERISION COMPLETE INTERRUPT FLAG
00EE +1 225 AD0TM BIT ADC0CN.6 ; ADC 0 TRACK MODE
00EF +1 226 AD0EN BIT ADC0CN.7 ; ADC 0 ENABLE
+1 227 ;
+1 228 ; SPI0CN F8H
00F8 +1 229 SPIEN BIT SPI0CN.0 ; SPI 0 SPI ENABLE
00F9 +1 230 MSTEN BIT SPI0CN.1 ; SPI 0 MASTER ENABLE
00FA +1 231 SLVSEL BIT SPI0CN.2 ; SPI 0 SLAVE SELECT
00FB +1 232 TXBSY BIT SPI0CN.3 ; SPI 0 TX BUSY FLAG
00FC +1 233 RXOVRN BIT SPI0CN.4 ; SPI 0 RX OVERRUN FLAG
00FD +1 234 MODF BIT SPI0CN.5 ; SPI 0 MODE FAULT FLAG
00FE +1 235 WCOL BIT SPI0CN.6 ; SPI 0 WRITE COLLISION FLAG
00FF +1 236 SPIF BIT SPI0CN.7 ; SPI 0 INTERRUPT FLAG
0040 237 MTD EQU 40H ;設(shè)接收緩沖首地址為40H
0040 238 MRD EQU 40H ;設(shè)發(fā)送緩沖首地址為40H
0000 239 ORG 0
0000 2100 240 AJMP MAIN
0100 241 ORG 100H
0100 242 MAIN:
0100 75FFDE 243 MOV WDTCN, #0DEh ;關(guān)看門狗定時器
0103 75FFAD 244 MOV WDTCN, #0ADh
0106 12014E 245 LCALL UARTINT
0109 D292 246 SETB P1.2 ;P1.2=1,實驗電路處于接收串行示菔淙氳淖刺?? 快捷鍵說明
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