?? sdr_sdram_tb.vhd
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--###############################################################################
--
-- LOGIC CORE: SDR SDRAM Controller test bench
-- MODULE NAME: sdr_sdram_tb()
-- COMPANY: Altera Corporation
-- www.altera.com
--
-- REVISION HISTORY:
--
-- Revision 1.0 06/06/2000 Description: Initial Release.
-- Revision 1.1 07/12/2000 Modified to support burst terminate and precharge
-- during full page accesses.
--
-- FUNCTIONAL DESCRIPTION:
--
-- This module is the test bench for the SDR SDRAM controller.
--
-- Copyright (C) 1991-2000 Altera Corporation
--
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library arithmetic;
--use arithmetic.std_logic_arith.all;
entity sdr_sdram_tb is
generic (
ASIZE : integer := 23;
DSIZE : integer := 32;
ROWSIZE : integer := 12;
COLSIZE : integer := 9;
BANKSIZE : integer := 2;
ROWSTART : integer := 9;
COLSTART : integer := 0;
BANKSTART : integer := 20
);
end sdr_sdram_tb;
architecture rtl of sdr_sdram_tb is
component sdr_sdram
port (
CLK : in std_logic; --System Clock
RESET_N : in std_logic; --System Reset
ADDR : in std_logic_vector(ASIZE-1 downto 0); --Address for controller requests
CMD : in std_logic_vector(2 downto 0); --Controller command
CMDACK : out std_logic; --Controller command acknowledgement
DATAIN : in std_logic_vector(DSIZE-1 downto 0); --Data input
DATAOUT : out std_logic_vector(DSIZE-1 downto 0); --Data output
DM : in std_logic_vector(DSIZE/8-1 downto 0); --Data mask input
SA : out std_logic_vector(11 downto 0); --SDRAM address output
BA : out std_logic_vector(1 downto 0); --SDRAM bank address
CS_N : out std_logic_vector(1 downto 0); --SDRAM Chip Selects
CKE : out std_logic; --SDRAM clock enable
RAS_N : out std_logic; --SDRAM Row address Strobe
CAS_N : out std_logic; --SDRAM Column address Strobe
WE_N : out std_logic; --SDRAM write enable
DQ : inout std_logic_vector(DSIZE-1 downto 0); --SDRAM data bus
DQM : out std_logic_vector(DSIZE/8-1 downto 0) --SDRAM data mask lines
);
end component;
component mt48lc8m16a2
PORT (
Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '0';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '0';
Cas_n : IN STD_LOGIC := '0';
We_n : IN STD_LOGIC := '0';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0')
);
END component;
signal clk : std_logic := '0';
signal clk2 : std_logic := '0';
signal reset_n : std_logic;
signal sa : std_logic_vector(11 downto 0);
signal ba : std_logic_vector(1 downto 0);
signal cs_n : std_logic_vector(1 downto 0);
signal cke : std_logic;
signal ras_n : std_logic;
signal cas_n : std_logic;
signal we_n : std_logic;
signal cmd : std_logic_vector(2 downto 0);
signal cmdack : std_logic;
signal addr : std_logic_vector(ASIZE-1 downto 0);
signal datain : std_logic_vector(DSIZE-1 downto 0);
signal dataout : std_logic_vector(DSIZE-1 downto 0);
signal dm : std_logic_vector(DSIZE/8-1 downto 0);
signal dq : std_logic_vector(DSIZE-1 downto 0);
signal dqm : std_logic_vector(DSIZE/8-1 downto 0);
signal test_addr : std_logic_vector(ASIZE-1 downto 0);
signal test_data : std_logic_vector(DSIZE-1 downto 0);
signal y : std_logic_vector(2 downto 0);
signal z : std_logic_vector(1 downto 0);
-- write_burst(start_data, start_addr, bl, rcd, mask, addr, dataout, dqm, cmdack, cmd)
--
-- This task performs a write access of size BL
-- at SDRAM address to the SDRAM controller
--
-- start_data : Starting value for the burst write sequence. The write burst procedure
-- simply increments the data values from the start_data value.
-- start_addr : Address in SDRAM to start the burst access
-- bl : bl is the burst length the sdram devices have been configured for.
-- rcd : rcd value that was set during configuration
-- mask : Byte data mask for all cycles in the burst.
-- addr : Address output
-- dataout : Data output
-- dqm : data mask output
-- cmdack : Command ack input
-- cmd : Command output
procedure burst_write (
start_data: std_logic_vector(DSIZE-1 downto 0);
start_addr: std_logic_vector(ASIZE-1 downto 0);
bl : integer;
rcd : integer;
mask : std_logic_vector(DSIZE/8-1 downto 0);
signal addr: out std_logic_vector(ASIZE-1 downto 0);
signal dataout: out std_logic_vector(DSIZE-1 downto 0);
signal dqm: out std_logic_vector(DSIZE/8-1 downto 0);
signal cmdack: std_logic;
signal cmd: out std_logic_vector(2 downto 0)) is
variable i : integer;
begin
wait until (CLK'event and CLK = '1');
wait for 1 ns;
cmd <= "010"; -- issued a WRITEA command
addr <= start_addr;
dataout <= start_data; -- issue the first data value
dqm <= mask;
wait until (cmdack = '1'); -- wait for a ack from the controller
wait until (CLK'event and CLK = '1');
wait for 1 ns;
cmd <= "000"; -- NOP the commmand input
for i in 1 to rcd-2 loop -- wait for RAS to CAS to expire
wait until (CLK'event and CLK = '1');
wait for 1 ns;
end loop;
for i in 1 to bl loop -- loop from 1 to bl
dataout <= start_data + i; -- clock the data into the controller
wait until (CLK'event and CLK = '1');
wait for 1 ns;
end loop;
dqm <= "0000";
end burst_write;
-- burst_read(address, start_value, CL, RCD, BL)
--
-- This task performs a read access of size BL
-- at SDRAM address to the SDRAM controller
--
-- start_data : Starting value for the burst read sequence. The read burst task
-- simply increments and compares the data values from the start_value.
-- start_addr : Address in SDRAM to start the burst access.
-- bl : bl is the burst length the sdram devices have been configured for.
-- cl : CAS latency the sdram devices have been configured for.
-- rcd : rcd value the controller has been configured for.
-- addr : Address output
-- datain : Data input
-- cmdack : Command ack input
-- cmd : Command output
procedure burst_read (
start_data: std_logic_vector(DSIZE-1 downto 0);
start_addr: std_logic_vector(ASIZE-1 downto 0);
bl : integer;
cl : integer;
rcd : integer;
signal addr: out std_logic_vector(ASIZE-1 downto 0);
signal datain: std_logic_vector(DSIZE-1 downto 0);
signal cmdack: std_logic;
signal cmd: out std_logic_vector(2 downto 0)) is
variable i: std_logic_vector(3 downto 0) := "0000";
begin
wait until (CLK'event and CLK = '1');
wait for 1 ns;
cmd <= "001"; -- issue a READA command
addr <= start_addr;
wait until (cmdack = '1'); -- wait for command ack
wait until (CLK'event and CLK = '1');
wait for 1 ns;
cmd <= "000"; -- NOP the command input
for i in 1 to (cl+rcd+1) loop -- wait for RAS to CAS and cl to expire
wait until (CLK'event and CLK = '1');
end loop;
for i in 1 to bl loop -- loop from 1 to burst length(BL),
wait until (CLK'event and CLK = '1'); -- collecting and comparing the data
-- wait for 3 ns;
if (datain /= start_data + i - 1 ) then
assert false
REPORT "read data mis-match"
SEVERITY FAILURE;
end if;
end loop;
end burst_read;
-- page_write_burst(address, start_value, data_mask, RCD, len, dataout, addr, dqm, cmd, cmdack)
--
-- This task performs a page write burst access of size length
-- at SDRAM address to the SDRAM controller
--
-- address : Address in SDRAM to start the burst access
-- start_value : Starting value for the burst write sequence. The write burst task
-- simply increments the data values from the start_value.
-- data_mask : Byte data mask for all cycles in the burst.
-- rcd : RCD value that was set during configuration
-- len : burst length of the access.
-- dataout : data output
-- addr : address output
-- dqm : data mask output
-- cmd : command output
-- cmdack : comand ack input
procedure page_write_burst(
address : std_logic_vector(ASIZE-1 downto 0);
start_value : std_logic_vector(DSIZE-1 downto 0);
data_mask : std_logic_vector(DSIZE/8-1 downto 0);
rcd : integer;
len : integer;
signal dataout : out std_logic_vector(DSIZE-1 downto 0);
signal addr : out std_logic_vector(ASIZE-1 downto 0);
signal dqm : out std_logic_vector(DSIZE/8-1 downto 0);
signal cmd : out std_logic_vector(2 downto 0);
signal cmdack : std_logic
) is
variable i : integer;
begin
wait until (CLK'event and CLK = '1');
wait for 1 ns;
addr <= address;
cmd <= "010";
dataout <= start_value;
dqm <= data_mask;
wait until (cmdack = '1'); -- wait for command ack
wait until (CLK'event and CLK = '1');
wait for 1 ns;
cmd <= "000";
for i in 1 to rcd-2 loop -- wait for rcd to pass
wait until (CLK'event and CLK = '1');
end loop;
wait for 1 ns;
for i in 1 to len-3 loop -- burst out len data cycles
dataout <= start_value + i;
wait until (CLK'event and CLK = '1');
wait for 1 ns;
end loop;
dataout <= start_value + len-2; --keep incrementing the data value
cmd <= "100"; -- issue a terminate command to terminate the page burst
wait until (CLK'event and CLK = '1');
wait for 1 ns;
dataout <= start_value + len-1; --increment the data one more
wait until (cmdack = '1'); -- Wait for the controller to ack the command
wait until (CLK'event and CLK = '1');
wait for 1 ns;
cmd <= "000"; -- Clear the command by issuing a NOP
dqm <= "0000";
wait for 200 ns;
cmd <= "100"; -- close the bank with a precharge
wait until (cmdack = '1');
wait until (CLK'event and CLK = '1');
wait for 1 ns;
cmd <= "000";
-- page_read_burst(address, start_value, cl, rcd, len, addr, datain, cmd, cmdack)
--
-- This task performs a page read access of size length
-- at SDRAM address to the SDRAM controller
--
-- address : Address in SDRAM to start the burst access
-- start_value : Starting value for the burst read sequence. The read burst task
-- simply increments and compares the data values from the start_value.
-- cl : CAS latency the sdram devices have been configured for.
-- rcd : rcd value the controller has been configured for.
-- len : burst length of the access.
-- addr : address output.
-- datain : data input;
-- cmd : command output;
-- cmdack : command ack;
procedure page_read_burst(
address : std_logic_vector(ASIZE-1 downto 0);
start_value : std_logic_vector(DSIZE-1 downto 0);
cl : integer;
rcd : integer;
len : integer;
signal addr : out std_logic_vector(ASIZE-1 downto 0);
signal datain : std_logic_vector(DSIZE-1 downto 0);
signal cmd : out std_logic_vector(2 downto 0);
signal cmdack : std_logic
) is
variable i : integer;
begin
wait until (CLK'event and CLK = '1');
wait for 1 ns;
addr <= address;
cmd <= "001"; -- issue a read command to the controller
wait until (cmdack = '1'); -- wait for the controller to ack
wait until (CLK'event and CLK = '1');
wait for 1 ns;
cmd <= "000"; -- NOP on the command input
for i in 1 to (CL+RCD) loop -- Wait for activate and cas latency delays
wait until (CLK'event and CLK = '1');
end loop;
for i in 1 to len loop -- loop and collect the data
wait until (CLK'event and CLK = '1');
wait for 3 ns;
if (i = (len-cl-5)) then
cmd <= "100"; -- Terminate the page burst
end if;
if (cmdack = '1') then
cmd<="000"; -- end the precharge command once the controller has ack'd
end if;
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