#include <stdio.h>
#include <stdlib.h>
#include "../inc/tc.h"
#include "../inc/sdram.h"

void delay(unsigned int t)
{
   while(t--);   
}
void main()
{
  unsigned short  Recieve[0x100][0x200]={0};  
  
 // unsigned char* buffer = (unsigned char*)malloc(100);    
 //unsigned char Recieve[20]={0};
  unsigned int i = 0;  
    
  while(1)
  {
    //for(i=0;i<SDRAM_MAXSIZE/16;i++)
    for(i=0;i<100;i++)
    {
     //AT91F_SDRAM_Write(i , i%10);
    }      
   
    for(i=0;i<200;i++)
    {
      Recieve[0][i] = AT91F_SDRAM_Read(i);   
    }  
  }
  }


//*----------------------------------------------------------------------------
//* \fn    AT91F_InitSdram
//* \brief Init EBI and SDRAM controller for MT48LC16M16A2
//*----------------------------------------------------------------------------
void AT91F_InitSdram (void)
{
    volatile unsigned int i;
    AT91PS_SDRC psdrc = AT91C_BASE_SDRC;
    // Init the EBI for SDRAM
    AT91C_BASE_EBI -> EBI_CSA =  AT91C_EBI_CS1A_SDRAMC; // Chip Select is assigned to SDRAM 
                                                  // controller
    //Configure PIO for EBI CS1
    AT91F_EBI_SDRAM_CfgPIO();
    //***  Step 1  ***
    // Set Configuration Register
    psdrc->SDRC_CR =  AT91C_SDRC_NC_9|           // 9  bits Column Addressing: 512 (A0-A8)
                                                 // AT91C_SDRC_NC_9
                      AT91C_SDRC_NR_13|           // 13 bits Row Addressing     8K (A0-12)
                                                 // AT91C_SDRC_NR_13
                      AT91C_SDRC_CAS_2|           // Micron MT48LC16M16A2-75(100MHz) needs CAS 2
                      AT91C_SDRC_NB_4_BANKS|      // 4 banks
                      AT91C_SDRC_TWR_2|        
                      AT91C_SDRC_TRC_4|        
                      AT91C_SDRC_TRP_2|        
                      AT91C_SDRC_TRCD_2|       
                      AT91C_SDRC_TRAS_3|       
                      AT91C_SDRC_TXSR_4 ;
    //***  Step 2  ***
    // Wait 200us (not needed since the system starts on slow clock)
    delay(400);
    //***  Step 3  ***
    // NOP Command
    psdrc->SDRC_MR = AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_NOP_CMD;// Set NOP
    *AT91C_SDRAM_BASE = 0x00000000;                                   // Perform NOP
    //***  Step 4  ***
    //All Banks Precharge Command
        psdrc->SDRC_MR = AT91C_SDRC_DBW_16_BITS | 0x00000002;        // Set PRCHG AL
    *AT91C_SDRAM_BASE= 0x00000000;                                    // Perform PRCHG
    //***  Step 5  ***
    //8 Refresh Command
    psdrc->SDRC_MR = AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;// Set 1st CBR
    *AT91C_SDRAM_BASE = 0x00000000;                                        // Perform CBR
    psdrc->SDRC_MR = AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;// Set 2nd CBR
    *AT91C_SDRAM_BASE = 0x00000000;                                        // Perform CBR
    psdrc->SDRC_MR= AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;// Set 3rd CBR
    *AT91C_SDRAM_BASE = 0x00000000;                                        // Perform CBR
    psdrc->SDRC_MR= AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;// Set 4th CBR
    *AT91C_SDRAM_BASE = 0x00000000;                                        // Perform CBR
    psdrc->SDRC_MR= AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;// Set 5th CBR
    *AT91C_SDRAM_BASE = 0x00000000;                                        // Perform CBR
    psdrc->SDRC_MR= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD;    // Set 6th CBR
    *AT91C_SDRAM_BASE = 0x00000000;                                        // Perform CBR
    psdrc->SDRC_MR= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD;    // Set 7th CBR
    *AT91C_SDRAM_BASE = 0x00000000;                                        // Perform CBR
    psdrc->SDRC_MR= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD;    // Set 8th CBR
    *AT91C_SDRAM_BASE = 0x00000000;                                        // Perform CBR
    //***  Step 6  ***
    //Mode Register Command
    psdrc->SDRC_MR= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_LMR_CMD;     // Set LMR operation
    *AT91C_SDRAM_BASE = 0x00000000;                                           // Perform LMR burst=1,
                                                                   // lat=2
    //***  Step 7  ***
    //Normal Mode Command
        psdrc->SDRC_MR= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_NORMAL_CMD;  // Set Normal mode
                                                                      // 16 bits
    *AT91C_SDRAM_BASE= 0x00000000;                                        // Perform Normal mode
    //***  Step 8  ***
    // Set Refresh Timer
    psdrc->SDRC_TR =AT91C_SDRC_TR_TIME;
}

void AT91F_EBI_SDRAM_CfgPIO(void)
{
   //PIOB->PIO_ASR = ~0 ;
   AT91PS_PIO PIOA = AT91C_BASE_PIOA;
   AT91PS_PIO PIOB = AT91C_BASE_PIOB;
   AT91PS_PIO PIOC = AT91C_BASE_PIOC;
   PIOA->PIO_PDR = PA23_B_NWR1|                 //out of PIO control 
                   PA24_B_SDA10|
                   PA25_B_SDCKE|
                   PA26_B_SDCS|
                   PA27_B_SDWE|
                   PA28_B_CAS|
                   PA29_B_RAS|
                   PA16_B_BA0|
                   PA17_B_BA1;                    
   PIOA->PIO_BSR = PA23_B_NWR1|                 //set the control command
                   PA24_B_SDA10|
                   PA25_B_SDCKE|
                   PA26_B_SDCS|
                   PA27_B_SDWE|
                   PA28_B_CAS|
                   PA29_B_RAS|
                   PA16_B_BA0|
                   PA17_B_BA1;          
   PIOB->PIO_PDR = PIOB_B_ADDRESS;               //out of PIO control 
   PIOB->PIO_BSR = PIOB_B_ADDRESS;               //set the address line
   PIOC->PIO_PDR = PIOC_A_DATA ;                 //out of PIO control 
   PIOC->PIO_ASR = PIOC_A_DATA ;                 //set the address line
}

void AT91F_SDRAM_Write(unsigned int Addr ,unsigned char Data)
{
  *(AT91C_SDRAM_BASE + Addr)= Data;
}

unsigned char AT91F_SDRAM_Read(unsigned int Addr)
{
  return( *(AT91C_SDRAM_BASE + Addr));
}