/* * * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] * *  Extended 3 / 2005 by Hartmut Hackmann to support various *  cards with the tda10046 DVB-T channel decoder * *  This program is free software; you can redistribute it and/or modify *  it under the terms of the GNU General Public License as published by *  the Free Software Foundation; either version 2 of the License, or *  (at your option) any later version. * *  This program is distributed in the hope that it will be useful, *  but WITHOUT ANY WARRANTY; without even the implied warranty of *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the *  GNU General Public License for more details. * *  You should have received a copy of the GNU General Public License *  along with this program; if not, write to the Free Software *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */#include <linux/init.h>#include <linux/list.h>#include <linux/module.h>#include <linux/kernel.h>#include <linux/slab.h>#include <linux/delay.h>#include <linux/kthread.h>#include <linux/suspend.h>#include "compat.h"#include "saa7134-reg.h"#include "saa7134.h"#include <media/v4l2-common.h>#include "dvb-pll.h"#ifdef HAVE_MT352# include "mt352.h"# include "mt352_priv.h" /* FIXME */#endif#ifdef HAVE_TDA1004X# include "tda1004x.h"#endif#ifdef HAVE_NXT200X# include "nxt200x.h"#endifMODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");MODULE_LICENSE("GPL");static unsigned int antenna_pwr = 0;module_param(antenna_pwr, int, 0444);MODULE_PARM_DESC(antenna_pwr,"enable antenna power (Pinnacle 300i)");/* ------------------------------------------------------------------ */#ifdef HAVE_MT352static int pinnacle_antenna_pwr(struct saa7134_dev *dev, int on){	u32 ok;	if (!on) {		saa_setl(SAA7134_GPIO_GPMODE0 >> 2,     (1 << 26));		saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26));		return 0;	}	saa_setl(SAA7134_GPIO_GPMODE0 >> 2,     (1 << 26));	saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2,   (1 << 26));	udelay(10);	saa_setl(SAA7134_GPIO_GPMODE0 >> 2,     (1 << 28));	saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28));	udelay(10);	saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2,   (1 << 28));	udelay(10);	ok = saa_readl(SAA7134_GPIO_GPSTATUS0) & (1 << 27);	printk("%s: %s %s\n", dev->name, __FUNCTION__,	       ok ? "on" : "off");	if (!ok)		saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2,   (1 << 26));	return ok;}static int mt352_pinnacle_init(struct dvb_frontend* fe){	static u8 clock_config []  = { CLOCK_CTL,  0x3d, 0x28 };	static u8 reset []         = { RESET,      0x80 };	static u8 adc_ctl_1_cfg [] = { ADC_CTL_1,  0x40 };	static u8 agc_cfg []       = { AGC_TARGET, 0x28, 0xa0 };	static u8 capt_range_cfg[] = { CAPT_RANGE, 0x31 };	static u8 fsm_ctl_cfg[]    = { 0x7b,       0x04 };	static u8 gpp_ctl_cfg []   = { GPP_CTL,    0x0f };	static u8 scan_ctl_cfg []  = { SCAN_CTL,   0x0d };	static u8 irq_cfg []       = { INTERRUPT_EN_0, 0x00, 0x00, 0x00, 0x00 };	struct saa7134_dev *dev= fe->dvb->priv;	printk("%s: %s called\n",dev->name,__FUNCTION__);	mt352_write(fe, clock_config,   sizeof(clock_config));	udelay(200);	mt352_write(fe, reset,          sizeof(reset));	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));	mt352_write(fe, gpp_ctl_cfg,    sizeof(gpp_ctl_cfg));	mt352_write(fe, fsm_ctl_cfg,    sizeof(fsm_ctl_cfg));	mt352_write(fe, scan_ctl_cfg,   sizeof(scan_ctl_cfg));	mt352_write(fe, irq_cfg,        sizeof(irq_cfg));	return 0;}static int mt352_aver777_init(struct dvb_frontend* fe){	static u8 clock_config []  = { CLOCK_CTL,  0x38, 0x2d };	static u8 reset []         = { RESET,      0x80 };	static u8 adc_ctl_1_cfg [] = { ADC_CTL_1,  0x40 };	static u8 agc_cfg []       = { AGC_TARGET, 0x28, 0xa0 };	static u8 capt_range_cfg[] = { CAPT_RANGE, 0x33 };	mt352_write(fe, clock_config,   sizeof(clock_config));	udelay(200);	mt352_write(fe, reset,          sizeof(reset));	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));	return 0;}static int mt352_pinnacle_pll_set(struct dvb_frontend* fe,				  struct dvb_frontend_parameters* params,				  u8* pllbuf){	u8 off[] = { 0x00, 0xf1};	u8 on[]  = { 0x00, 0x71};	struct i2c_msg msg = {.addr=0x43, .flags=0, .buf=off, .len = sizeof(off)};	struct saa7134_dev *dev = fe->dvb->priv;	struct v4l2_frequency f;	/* set frequency (mt2050) */	f.tuner     = 0;	f.type      = V4L2_TUNER_DIGITAL_TV;	f.frequency = params->frequency / 1000 * 16 / 1000;	i2c_transfer(&dev->i2c_adap, &msg, 1);	saa7134_i2c_call_clients(dev,VIDIOC_S_FREQUENCY,&f);	msg.buf = on;	i2c_transfer(&dev->i2c_adap, &msg, 1);	pinnacle_antenna_pwr(dev, antenna_pwr);	/* mt352 setup */	mt352_pinnacle_init(fe);	pllbuf[0] = 0xc2;	pllbuf[1] = 0x00;	pllbuf[2] = 0x00;	pllbuf[3] = 0x80;	pllbuf[4] = 0x00;	return 0;}static int mt352_aver777_pll_set(struct dvb_frontend *fe, struct dvb_frontend_parameters *params, u8* pllbuf){	pllbuf[0] = 0xc2;	dvb_pll_configure(&dvb_pll_philips_td1316, pllbuf+1,			  params->frequency,			  params->u.ofdm.bandwidth);	return 0;}static struct mt352_config pinnacle_300i = {	.demod_address = 0x3c >> 1,	.adc_clock     = 20333,	.if2           = 36150,	.no_tuner      = 1,	.demod_init    = mt352_pinnacle_init,	.pll_set       = mt352_pinnacle_pll_set,};static struct mt352_config avermedia_777 = {	.demod_address = 0xf,	.demod_init    = mt352_aver777_init,	.pll_set       = mt352_aver777_pll_set,};#endif/* ------------------------------------------------------------------ */#ifdef HAVE_TDA1004Xstatic int philips_tda6651_pll_set(u8 addr, struct dvb_frontend *fe, struct dvb_frontend_parameters *params){	struct saa7134_dev *dev = fe->dvb->priv;	u8 tuner_buf[4];	struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tuner_buf,.len =			sizeof(tuner_buf) };	int tuner_frequency = 0;	u8 band, cp, filter;	/* determine charge pump */	tuner_frequency = params->frequency + 36166000;	if (tuner_frequency < 87000000)		return -EINVAL;	else if (tuner_frequency < 130000000)		cp = 3;	else if (tuner_frequency < 160000000)		cp = 5;	else if (tuner_frequency < 200000000)		cp = 6;	else if (tuner_frequency < 290000000)		cp = 3;	else if (tuner_frequency < 420000000)		cp = 5;	else if (tuner_frequency < 480000000)		cp = 6;	else if (tuner_frequency < 620000000)		cp = 3;	else if (tuner_frequency < 830000000)		cp = 5;	else if (tuner_frequency < 895000000)		cp = 7;	else		return -EINVAL;	/* determine band */	if (params->frequency < 49000000)		return -EINVAL;	else if (params->frequency < 161000000)		band = 1;	else if (params->frequency < 444000000)		band = 2;	else if (params->frequency < 861000000)		band = 4;	else		return -EINVAL;	/* setup PLL filter */	switch (params->u.ofdm.bandwidth) {	case BANDWIDTH_6_MHZ:		filter = 0;		break;	case BANDWIDTH_7_MHZ:		filter = 0;		break;	case BANDWIDTH_8_MHZ:		filter = 1;		break;	default:		return -EINVAL;	}	/* calculate divisor	 * ((36166000+((1000000/6)/2)) + Finput)/(1000000/6)	 */	tuner_frequency = (((params->frequency / 1000) * 6) + 217496) / 1000;	/* setup tuner buffer */	tuner_buf[0] = (tuner_frequency >> 8) & 0x7f;	tuner_buf[1] = tuner_frequency & 0xff;	tuner_buf[2] = 0xca;	tuner_buf[3] = (cp << 5) | (filter << 3) | band;	if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)		return -EIO;	msleep(1);	return 0;}static int philips_tda6651_pll_init(u8 addr, struct dvb_frontend *fe){	struct saa7134_dev *dev = fe->dvb->priv;	static u8 tu1216_init[] = { 0x0b, 0xf5, 0x85, 0xab };	struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tu1216_init,.len = sizeof(tu1216_init) };	/* setup PLL configuration */	if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)		return -EIO;	msleep(1);	return 0;}/* ------------------------------------------------------------------ */static int philips_tu1216_pll_60_init(struct dvb_frontend *fe){	return philips_tda6651_pll_init(0x60, fe);}static int philips_tu1216_pll_60_set(struct dvb_frontend *fe, struct dvb_frontend_parameters *params){	return philips_tda6651_pll_set(0x60, fe, params);}static int philips_tu1216_request_firmware(struct dvb_frontend *fe,					   const struct firmware **fw, char *name){	struct saa7134_dev *dev = fe->dvb->priv;	return request_firmware(fw, name, &dev->pci->dev);}static struct tda1004x_config philips_tu1216_60_config = {	.demod_address = 0x8,	.invert        = 1,	.invert_oclk   = 0,	.xtal_freq     = TDA10046_XTAL_4M,	.agc_config    = TDA10046_AGC_DEFAULT,	.if_freq       = TDA10046_FREQ_3617,	.pll_init      = philips_tu1216_pll_60_init,	.pll_set       = philips_tu1216_pll_60_set,	.pll_sleep     = NULL,	.request_firmware = philips_tu1216_request_firmware,};/* ------------------------------------------------------------------ */static int philips_tu1216_pll_61_init(struct dvb_frontend *fe){	return philips_tda6651_pll_init(0x61, fe);}static int philips_tu1216_pll_61_set(struct dvb_frontend *fe, struct dvb_frontend_parameters *params){	return philips_tda6651_pll_set(0x61, fe, params);}static struct tda1004x_config philips_tu1216_61_config = {	.demod_address = 0x8,	.invert        = 1,	.invert_oclk   = 0,	.xtal_freq     = TDA10046_XTAL_4M,	.agc_config    = TDA10046_AGC_DEFAULT,	.if_freq       = TDA10046_FREQ_3617,	.pll_init      = philips_tu1216_pll_61_init,	.pll_set       = philips_tu1216_pll_61_set,	.pll_sleep     = NULL,	.request_firmware = philips_tu1216_request_firmware,};/* ------------------------------------------------------------------ */static int philips_europa_pll_init(struct dvb_frontend *fe){	struct saa7134_dev *dev = fe->dvb->priv;	static u8 msg[] = { 0x0b, 0xf5, 0x86, 0xab };	struct i2c_msg init_msg = {.addr = 0x61,.flags = 0,.buf = msg,.len = sizeof(msg) };	/* setup PLL configuration */	if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1)		return -EIO;	msleep(1);	/* switch the board to dvb mode */	init_msg.addr = 0x43;	init_msg.len  = 0x02;	msg[0] = 0x00;	msg[1] = 0x40;	if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1)		return -EIO;	return 0;}static int philips_td1316_pll_set(struct dvb_frontend *fe, struct dvb_frontend_parameters *params){	return philips_tda6651_pll_set(0x61, fe, params);}