/* * sound/arm/omap/omap2-audio-twl4030.h * * The Audio Specific Definitions for TWL4030 ES1.0 chip * * Copyright (C) 2007 Texas Instruments, Inc. * * This package is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. * * History: *  ------- *  2006-01-18 Nishanth Menon - Created *  2007-04-16 Leonides Martinez - Additional controls info */#define __OMAP_AUDIO_TWL4030_H__/**************************************** *  AUDIO_VOICE ****************************************//**** Register Definitions REG_BASE=0x0 DevAdd=0x49 *//*** CONVENTION: * REG_xxx - Register offset * BIT_xxx - Bit field bit location * BIT_xxx_M - Mask for that Field. * Valid values are posted next to the bit definition */#define REG_CODEC_MODE                           (0x1)#define REG_OPTION                               (0x2)#define REG_MICBIAS_CTL                          (0x4)#define REG_ANAMICL                              (0x5)#define REG_ANAMICR                              (0x6)#define REG_AVADC_CTL                            (0x7)#define REG_ADCMICSEL                            (0x8)#define REG_DIGMIXING                            (0x9)#define REG_ATXL1PGA                             (0xA)#define REG_ATXR1PGA                             (0xB)#define REG_AVTXL2PGA                            (0xC)#define REG_AVTXR2PGA                            (0xD)#define REG_AUDIO_IF                             (0xE)#define REG_VOICE_IF                             (0xF)#define REG_ARXR1PGA                             (0x10)#define REG_ARXL1PGA                             (0x11)#define REG_ARXR2PGA                             (0x12)#define REG_ARXL2PGA                             (0x13)#define REG_VRXPGA                               (0x14)#define REG_VSTPGA                               (0x15)#define REG_VRX2ARXPGA                           (0x16)#define REG_AVDAC_CTL                            (0x17)#define REG_ARX2VTXPGA                           (0x18)#define REG_ARXL1_APGA_CTL                       (0x19)#define REG_ARXR1_APGA_CTL                       (0x1A)#define REG_ARXL2_APGA_CTL                       (0x1B)#define REG_ARXR2_APGA_CTL                       (0x1C)#define REG_ATX2ARXPGA                           (0x1D)#define REG_BT_IF                                (0x1E)#define REG_BTPGA                                (0x1F)#define REG_BTSTPGA                              (0x20)#define REG_EAR_CTL                              (0x21)#define REG_HS_SEL                               (0x22)#define REG_HS_GAIN_SET                          (0x23)#define REG_HS_POPN_SET                          (0x24)#define REG_PREDL_CTL                            (0x25)#define REG_PREDR_CTL                            (0x26)#define REG_PRECKL_CTL                           (0x27)#define REG_PRECKR_CTL                           (0x28)#define REG_HFL_CTL                              (0x29)#define REG_HFR_CTL                              (0x2A)#define REG_ALC_CTL                              (0x2B)#define REG_ALC_SET1                             (0x2C)#define REG_ALC_SET2                             (0x2D)#define REG_BOOST_CTL                            (0x2E)#define REG_SOFTVOL_CTL                          (0x2F)#define REG_DTMF_FREQSEL                         (0x30)#define REG_DTMF_TONEXT1H                        (0x31)#define REG_DTMF_TONEXT1L                        (0x32)#define REG_DTMF_TONEXT2H                        (0x33)#define REG_DTMF_TONEXT2L                        (0x34)#define REG_DTMF_TONOFF                          (0x35)#define REG_DTMF_WANONOFF                        (0x36)#define REG_I2S_RX_SCRAMBLE_H                    (0x37)#define REG_I2S_RX_SCRAMBLE_M                    (0x38)#define REG_I2S_RX_SCRAMBLE_L                    (0x39)#define REG_APLL_CTL                             (0x3A)#define REG_DTMF_CTL                             (0x3B)#define REG_DTMF_PGA_CTL2                        (0x3C)#define REG_DTMF_PGA_CTL1                        (0x3D)#define REG_MISC_SET_1                           (0x3E)#define REG_PCMBTMUX                             (0x3F)#define REG_RX_PATH_SEL                          (0x43)#define REG_VDL_APGA_CTL                         (0x44)#define REG_VIBRA_CTL                            (0x45)#define REG_VIBRA_SET                            (0x46)#define REG_VIBRA_PWM_SET                        (0x47)#define REG_ANAMIC_GAIN                          (0x48)#define REG_MISC_SET_2                           (0x49)#define MAX_NUM_REG_CLEAN                        (REG_MISC_SET_2 - REG_CODEC_MODE)/**** BitField Definitions *//* CODEC_MODE Fields */#define BIT_CODEC_MODE_OPT_MODE                  (0x000)#define BIT_CODEC_MODE_OPT_MODE_M                (0x00000001)#define CODEC_OPTION_1                           (0x1)#define CODEC_OPTION_2                           (0x0)#define BIT_CODEC_MODE_CODECPDZ                  (0x001)#define BIT_CODEC_MODE_CODECPDZ_M                (0x00000002)#define BIT_CODEC_MODE_SPARE                     (0x002)#define BIT_CODEC_MODE_SPARE_M                   (0x00000004)#define BIT_CODEC_MODE_SEL_16K                   (0x003)#define BIT_CODEC_MODE_SEL_16K_M                 (0x00000008)#define VOICE_MODE_RATE_08_000K                  (0x0)#define VOICE_MODE_RATE_16_000K                  (0x1)#define BIT_CODEC_MODE_APLL_RATE                 (0x004)#define BIT_CODEC_MODE_APLL_RATE_M               (0x000000F0)#define AUDIO_MODE_RATE_08_000                   (0x0)#define AUDIO_MODE_RATE_11_025                   (0x1)#define AUDIO_MODE_RATE_12_000                   (0x2)#define AUDIO_MODE_RATE_16_000                   (0x4)#define AUDIO_MODE_RATE_22_050                   (0x5)#define AUDIO_MODE_RATE_24_000                   (0x6)#define AUDIO_MODE_RATE_32_000                   (0x8)#define AUDIO_MODE_RATE_44_100                   (0x9)#define AUDIO_MODE_RATE_48_000                   (0xA)#define AUDIO_MODE_RATE_96_000                   (0xE)/* OPTION Fields */#define BIT_OPTION_ATXL1_EN                      (0x000)#define BIT_OPTION_ATXL1_EN_M                    (0x00000001)#define BIT_OPTION_ATXR1_EN                      (0x001)#define BIT_OPTION_ATXR1_EN_M                    (0x00000002)#define BIT_OPTION_ATXL2_VTXL_EN                 (0x002)#define BIT_OPTION_ATXL2_VTXL_EN_M               (0x00000004)#define BIT_OPTION_ATXR2_VTXR_EN                 (0x003)#define BIT_OPTION_ATXR2_VTXR_EN_M               (0x00000008)#define BIT_OPTION_ARXL1_VRX_EN                  (0x004)#define BIT_OPTION_ARXL1_VRX_EN_M                (0x00000010)#define BIT_OPTION_ARXR1_EN                      (0x005)#define BIT_OPTION_ARXR1_EN_M                    (0x00000020)#define BIT_OPTION_ARXL2_EN                      (0x006)#define BIT_OPTION_ARXL2_EN_M                    (0x00000040)#define BIT_OPTION_ARXR2_EN                      (0x007)#define BIT_OPTION_ARXR2_EN_M                    (0x00000080)/* MICBIAS_CTL Fields */#define BIT_MICBIAS_CTL_MICBIAS1_EN              (0x000)#define BIT_MICBIAS_CTL_MICBIAS1_EN_M            (0x00000001)#define BIT_MICBIAS_CTL_MICBIAS2_EN              (0x001)#define BIT_MICBIAS_CTL_MICBIAS2_EN_M            (0x00000002)#define BIT_MICBIAS_CTL_HSMICBIAS_EN             (0x002)#define BIT_MICBIAS_CTL_HSMICBIAS_EN_M           (0x00000004)#define BIT_MICBIAS_CTL_MICBIAS1_CTL             (0x005)#define BIT_MICBIAS_CTL_MICBIAS1_CTL_M           (0x00000020)#define BIT_MICBIAS_CTL_MICBIAS2_CTL             (0x006)#define BIT_MICBIAS_CTL_MICBIAS2_CTL_M           (0x00000040)#define BIT_MICBIAS_CTL_SPARE                    (0x007)#define BIT_MICBIAS_CTL_SPARE_M                  (0x00000080)/* ANAMICL Fields */#define BIT_ANAMICL_MAINMIC_EN                   (0x000)#define BIT_ANAMICL_MAINMIC_EN_M                 (0x00000001)#define BIT_ANAMICL_HSMIC_EN                     (0x001)#define BIT_ANAMICL_HSMIC_EN_M                   (0x00000002)#define BIT_ANAMICL_AUXL_EN                      (0x002)#define BIT_ANAMICL_AUXL_EN_M                    (0x00000004)#define BIT_ANAMICL_CKMIC_EN                     (0x003)#define BIT_ANAMICL_CKMIC_EN_M                   (0x00000008)#define BIT_ANAMICL_MICAMPL_EN                   (0x004)#define BIT_ANAMICL_MICAMPL_EN_M                 (0x00000010)#define BIT_ANAMICL_OFFSET_CNCL_SEL              (0x005)#define BIT_ANAMICL_OFFSET_CNCL_SEL_M            (0x00000060)#define BIT_ANAMICL_CNCL_OFFSET_START            (0x007)#define BIT_ANAMICL_CNCL_OFFSET_START_M          (0x00000080)/* ANAMICR Fields */#define BIT_ANAMICR_SUBMIC_EN                    (0x000)#define BIT_ANAMICR_SUBMIC_EN_M                  (0x00000001)#define BIT_ANAMICR_AUXR_EN                      (0x002)#define BIT_ANAMICR_AUXR_EN_M                    (0x00000004)#define BIT_ANAMICR_MICAMPR_EN                   (0x004)#define BIT_ANAMICR_MICAMPR_EN_M                 (0x00000010)/* AVADC_CTL Fields */#define BIT_AVADC_CTL_ADCR_EN                    (0x001)#define BIT_AVADC_CTL_ADCR_EN_M                  (0x00000002)#define BIT_AVADC_CTL_AVADC_CLK_PRIORITY         (0x002)#define BIT_AVADC_CTL_AVADC_CLK_PRIORITY_M       (0x00000004)#define BIT_AVADC_CTL_ADCL_EN                    (0x003)#define BIT_AVADC_CTL_ADCL_EN_M                  (0x00000008)/* ADCMICSEL Fields */#define BIT_ADCMICSEL_TX1IN_SEL                  (0x000)#define BIT_ADCMICSEL_TX1IN_SEL_M                (0x00000001)#define BIT_ADCMICSEL_DIGMIC0_EN                 (0x001)#define BIT_ADCMICSEL_DIGMIC0_EN_M               (0x00000002)#define BIT_ADCMICSEL_TX2IN_SEL                  (0x002)#define BIT_ADCMICSEL_TX2IN_SEL_M                (0x00000004)#define BIT_ADCMICSEL_DIGMIC1_EN                 (0x003)#define BIT_ADCMICSEL_DIGMIC1_EN_M               (0x00000008)/* DIGMIXING Fields */#define BIT_DIGMIXING_VTX_MIXING                 (0x002)#define BIT_DIGMIXING_VTX_MIXING_M               (0x0000000C)#define BIT_DIGMIXING_ARX2_MIXING                (0x004)#define BIT_DIGMIXING_ARX2_MIXING_M              (0x00000030)#define BIT_DIGMIXING_ARX1_MIXING                (0x006)#define BIT_DIGMIXING_ARX1_MIXING_M              (0x000000C0)#define INPUT_GAIN_MIN                           (0x00)#define INPUT_GAIN_MAX                           (0x1F)/* ATXL1PGA Fields */#define BIT_ATXL1PGA_ATXL1PGA_GAIN               (0x000)#define BIT_ATXL1PGA_ATXL1PGA_GAIN_M             (0x0000001F)/* ATXR1PGA Fields */#define BIT_ATXR1PGA_ATXR1PGA_GAIN               (0x000)#define BIT_ATXR1PGA_ATXR1PGA_GAIN_M             (0x0000001F)/* AVTXL2PGA Fields */#define BIT_AVTXL2PGA_AVTXL2PGA_GAIN             (0x000)#define BIT_AVTXL2PGA_AVTXL2PGA_GAIN_M           (0x0000001F)/* AVTXR2PGA Fields */#define BIT_AVTXR2PGA_AVTXR2PGA_GAIN             (0x000)#define BIT_AVTXR2PGA_AVTXR2PGA_GAIN_M           (0x0000001F)/* AUDIO_IF Fields */#define BIT_AUDIO_IF_AIF_EN                      (0x000)#define BIT_AUDIO_IF_AIF_EN_M                    (0x00000001)#define BIT_AUDIO_IF_CLK256FS_EN                 (0x001)#define BIT_AUDIO_IF_CLK256FS_EN_M               (0x00000002)#define BIT_AUDIO_IF_AIF_TRI_EN                  (0x002)#define BIT_AUDIO_IF_AIF_TRI_EN_M                (0x00000004)#define AUDIO_DATA_FORMAT_I2S                    (0x0)#define AUDIO_DATA_FORMAT_LJUST                  (0x1)#define AUDIO_DATA_FORMAT_RJUST                  (0x2)#define AUDIO_DATA_FORMAT_TDM                    (0x3)#define BIT_AUDIO_IF_AIF_FORMAT                  (0x003)#define BIT_AUDIO_IF_AIF_FORMAT_M                (0x00000018)#define AUDIO_DATA_WIDTH_16SAMPLE_16DATA         (0x0)#define AUDIO_DATA_WIDTH_32SAMPLE_16DATA         (0x2)#define AUDIO_DATA_WIDTH_32SAMPLE_24DATA         (0x3)#define BIT_AUDIO_IF_DATA_WIDTH                  (0x005)#define BIT_AUDIO_IF_DATA_WIDTH_M                (0x00000060)#define BIT_AUDIO_IF_AIF_SLAVE_EN                (0x007)#define BIT_AUDIO_IF_AIF_SLAVE_EN_M              (0x00000080)/* VOICE_IF Fields */#define BIT_VOICE_IF_VIF_EN                      (0x000)#define BIT_VOICE_IF_VIF_EN_M                    (0x00000001)#define BIT_VOICE_IF_VIF_SUB_EN                  (0x001)#define BIT_VOICE_IF_VIF_SUB_EN_M                (0x00000002)#define BIT_VOICE_IF_VIF_TRI_EN                  (0x002)#define BIT_VOICE_IF_VIF_TRI_EN_M                (0x00000004)#define BIT_VOICE_IF_VIF_FORMAT                  (0x003)#define BIT_VOICE_IF_VIF_FORMAT_M                (0x00000008)#define BIT_VOICE_IF_VIF_SWAP                    (0x004)#define BIT_VOICE_IF_VIF_SWAP_M                  (0x00000010)#define BIT_VOICE_IF_VIF_DOUT_EN                 (0x005)#define BIT_VOICE_IF_VIF_DOUT_EN_M               (0x00000020)#define BIT_VOICE_IF_VIF_DIN_EN                  (0x006)#define BIT_VOICE_IF_VIF_DIN_EN_M                (0x00000040)#define BIT_VOICE_IF_VIF_SLAVE_EN                (0x007)#define BIT_VOICE_IF_VIF_SLAVE_EN_M              (0x00000080)/* volume range */#define OUTPUT_GAIN_MIN                          (0x00)#define OUTPUT_GAIN_MAX                          (0x3F)#define AUDIO_OUTPUT_COARSE_GAIN_LOW             (0x0)#define AUDIO_OUTPUT_COARSE_GAIN_6DB             (0x1)#define AUDIO_OUTPUT_COARSE_GAIN_12DB            (0x2)/* ARXR1PGA Fields */#define BIT_ARXR1PGA_ARXR1PGA_FGAIN              (0x000)#define BIT_ARXR1PGA_ARXR1PGA_FGAIN_M            (0x0000003F)#define BIT_ARXR1PGA_ARXR1PGA_CGAIN              (0x006)#define BIT_ARXR1PGA_ARXR1PGA_CGAIN_M            (0x000000C0)/* ARXL1PGA Fields */#define BIT_ARXL1PGA_ARXL1PGA_FGAIN              (0x000)#define BIT_ARXL1PGA_ARXL1PGA_FGAIN_M            (0x0000003F)#define BIT_ARXL1PGA_ARXL1PGA_CGAIN              (0x006)#define BIT_ARXL1PGA_ARXL1PGA_CGAIN_M            (0x000000C0)/* ARXR2PGA Fields */#define BIT_ARXR2PGA_ARXR2PGA_FGAIN              (0x000)#define BIT_ARXR2PGA_ARXR2PGA_FGAIN_M            (0x0000003F)#define BIT_ARXR2PGA_ARXR2PGA_CGAIN              (0x006)#define BIT_ARXR2PGA_ARXR2PGA_CGAIN_M            (0x000000C0)/* ARXL2PGA Fields */