/********************************************************************
*
* Register definitions for the ADS7871 DAQ System
* Texas Instruments, Version 1.1
*
********************************************************************/

#ifndef __ADS787x
#define __ADS787x


/************************************************************
* Instruction Modes
************************************************************/
#define DIRECT              (0x80)
#define REGISTER            (0x00)


/************************************************************
* Start Conversion Instructions (Direct Mode)
************************************************************/
#define CONVST              (0x80)
#define GAIN01              (0x00)
#define GAIN02              (0x10)
#define GAIN04              (0x20)
#define GAIN05              (0x30)
#define GAIN08              (0x40)
#define GAIN10              (0x50)
#define GAIN16              (0x60)
#define GAIN20              (0x70)
#define CHANNEL             (0x00)  // See Channel Def. for REG 4 Below


/************************************************************
* Read/Write Instructions (Register Mode)
************************************************************/
#define WRITE               (0x00)
#define READ                (0x40)
#define WORD                (0x20)
#define BYTE                (0x00)
#define REG0                (0x00)
#define REG1                (0x01)
#define REG2                (0x02)
#define REG3                (0x03)
#define REG4                (0x04)
#define REG5                (0x05)
#define REG6                (0x06)
#define REG7                (0x07)
#define REG24               (0x18)
#define REG31               (0x1F)


/************************************************************
* Bits for ADC Output (Register 1)
************************************************************/
//LS Byte
#define ADC5               (0x80)
#define ADC4               (0x40)
#define ADC3               (0x20)
#define ADC2               (0x10)
#define ADC1               (0x08)
#define ADC0               (0x04)
#define OVR                (0x01)

//MS Byte
#define ADCD               (0x80)
#define ADCC               (0x40)
#define ADCB               (0x20)
#define ADCA               (0x10)
#define ADC9               (0x08)
#define ADC8               (0x04)
#define ADC7               (0x02)
#define ADC6               (0x01)

/************************************************************
* Bits for PGA Valid (Read Only Register 2)
************************************************************/
#define VLD5               (0x20)
#define VLD4               (0x10)
#define VLD3               (0x08)
#define VLD2               (0x04)
#define VLD1               (0x02)
#define VLD0               (0x01)

/************************************************************
* Bits for AD Control (Register 3)
************************************************************/
#define SM0                (0x40)
#define BIN                (0x20)
#define TWOS               (0x00)
#define MODE0              (0x00)
#define MODE1              (0x04)
#define MODE2              (0x08)
#define MODE3              (0x0C)
#define DIV0               (0x00)
#define DIV1               (0x01)
#define DIV2               (0x02)
#define DIV3               (0x03)

/************************************************************
* Bits for Gain/MUX Control (Register 4)
************************************************************/
#define CNV_BSY            (0x80)
#define PGA20              (0x70)
#define PGA16              (0x60)
#define PGA10              (0x50)
#define PGA8               (0x40)
#define PGA5               (0x30)
#define PGA4               (0x20)
#define PGA2               (0x10)
#define PGA1               (0x00)

//Channel Select
#define DIFF0              (0x00)
#define DIFF1              (0x01)
#define DIFF2              (0x02)
#define DIFF3              (0x03)
#define DIFF4              (0x04)
#define DIFF5              (0x05)
#define DIFF6              (0x06)
#define DIFF7              (0x07)
#define SING0              (0x08)
#define SING1              (0x09)
#define SING2              (0x0A)
#define SING3              (0x0B)
#define SING4              (0x0C)
#define SING5              (0x0D)
#define SING6              (0x0E)
#define SING7              (0x0F)

/************************************************************
* Bits for Register 5/6
************************************************************/
#define CNV                 (0x80)
#define IO3                 (0x08)
#define IO2                 (0x04)
#define IO1                 (0x02)
#define IO0                 (0x01)

/************************************************************
* Bits for Register 7
************************************************************/
#define OSCR                (0x20)
#define OSCE                (0x10)
#define REFE                (0x08)
#define BUFE                (0x04)
#define R2V                 (0x02)
#define RBG                 (0x01)

/************************************************************
* Bits for Register 24
************************************************************/
#define LSBA                      (0x80)
#define TWO_Wire_A                (0x40)
#define Eighty51_A                (0x20)
#define Eighty51_B                (0x04)
#define TWO_Wire_B                (0x02)
#define LSBB                      (0x01)

/************************************************************
* Bits for Register 31
************************************************************/
#define ID                  (0x01)


/************************************************************
* End of Modules
************************************************************/

#endif /* #ifndef __ADS787x */