#define S3C2410_GPC5            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)#define S3C2410_GPC5_INP	(0x00 << 10)#define S3C2410_GPC5_OUTP	(0x01 << 10)#define S3C2410_GPC5_LCDVF0	(0x02 << 10)#define S3C2400_GPC5_VD5   	(0x02 << 10)#define S3C2410_GPC6            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)#define S3C2410_GPC6_INP	(0x00 << 12)#define S3C2410_GPC6_OUTP	(0x01 << 12)#define S3C2410_GPC6_LCDVF1	(0x02 << 12)#define S3C2400_GPC6_VD6   	(0x02 << 12)#define S3C2410_GPC7            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)#define S3C2410_GPC7_INP	(0x00 << 14)#define S3C2410_GPC7_OUTP	(0x01 << 14)#define S3C2410_GPC7_LCDVF2	(0x02 << 14)#define S3C2400_GPC7_VD7   	(0x02 << 14)#define S3C2410_GPC8            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)#define S3C2410_GPC8_INP	(0x00 << 16)#define S3C2410_GPC8_OUTP	(0x01 << 16)#define S3C2410_GPC8_VD0	(0x02 << 16)#define S3C2400_GPC8_VD8	(0x02 << 16)#define S3C2410_GPC9            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)#define S3C2410_GPC9_INP	(0x00 << 18)#define S3C2410_GPC9_OUTP	(0x01 << 18)#define S3C2410_GPC9_VD1	(0x02 << 18)#define S3C2400_GPC9_VD9	(0x02 << 18)#define S3C2410_GPC10           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)#define S3C2410_GPC10_INP	(0x00 << 20)#define S3C2410_GPC10_OUTP	(0x01 << 20)#define S3C2410_GPC10_VD2	(0x02 << 20)#define S3C2400_GPC10_VD10	(0x02 << 20)#define S3C2410_GPC11           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)#define S3C2410_GPC11_INP	(0x00 << 22)#define S3C2410_GPC11_OUTP	(0x01 << 22)#define S3C2410_GPC11_VD3	(0x02 << 22)#define S3C2400_GPC11_VD11	(0x02 << 22)#define S3C2410_GPC12           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)#define S3C2410_GPC12_INP	(0x00 << 24)#define S3C2410_GPC12_OUTP	(0x01 << 24)#define S3C2410_GPC12_VD4	(0x02 << 24)#define S3C2400_GPC12_VD12	(0x02 << 24)#define S3C2410_GPC13           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)#define S3C2410_GPC13_INP	(0x00 << 26)#define S3C2410_GPC13_OUTP	(0x01 << 26)#define S3C2410_GPC13_VD5	(0x02 << 26)#define S3C2400_GPC13_VD13	(0x02 << 26)#define S3C2410_GPC14           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)#define S3C2410_GPC14_INP	(0x00 << 28)#define S3C2410_GPC14_OUTP	(0x01 << 28)#define S3C2410_GPC14_VD6	(0x02 << 28)#define S3C2400_GPC14_VD14	(0x02 << 28)#define S3C2410_GPC15           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)#define S3C2410_GPC15_INP	(0x00 << 30)#define S3C2410_GPC15_OUTP	(0x01 << 30)#define S3C2410_GPC15_VD7	(0x02 << 30)#define S3C2400_GPC15_VD15	(0x02 << 30)#define S3C2410_GPC_PUPDIS(x)  (1<<(x))/* * S3C2410: Port D consists of 16 GPIO/Special function * * almost identical setup to port b, but the special functions are mostly * to do with the video system's data. * * S3C2400: Port D consists of 11 GPIO/Special function * * almost identical setup to port c*/#define S3C2410_GPDCON	   S3C2410_GPIOREG(0x30)#define S3C2410_GPDDAT	   S3C2410_GPIOREG(0x34)#define S3C2410_GPDUP	   S3C2410_GPIOREG(0x38)#define S3C2400_GPDCON	   S3C2410_GPIOREG(0x20)#define S3C2400_GPDDAT	   S3C2410_GPIOREG(0x24)#define S3C2400_GPDUP	   S3C2410_GPIOREG(0x28)#define S3C2410_GPD0            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)#define S3C2410_GPD0_INP	(0x00 << 0)#define S3C2410_GPD0_OUTP	(0x01 << 0)#define S3C2410_GPD0_VD8	(0x02 << 0)#define S3C2400_GPD0_VFRAME	(0x02 << 0)#define S3C2410_GPD1            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)#define S3C2410_GPD1_INP	(0x00 << 2)#define S3C2410_GPD1_OUTP	(0x01 << 2)#define S3C2410_GPD1_VD9	(0x02 << 2)#define S3C2400_GPD1_VM		(0x02 << 2)#define S3C2410_GPD2            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)#define S3C2410_GPD2_INP	(0x00 << 4)#define S3C2410_GPD2_OUTP	(0x01 << 4)#define S3C2410_GPD2_VD10	(0x02 << 4)#define S3C2400_GPD2_VLINE	(0x02 << 4)#define S3C2410_GPD3            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)#define S3C2410_GPD3_INP	(0x00 << 6)#define S3C2410_GPD3_OUTP	(0x01 << 6)#define S3C2410_GPD3_VD11	(0x02 << 6)#define S3C2400_GPD3_VCLK	(0x02 << 6)#define S3C2410_GPD4            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)#define S3C2410_GPD4_INP	(0x00 << 8)#define S3C2410_GPD4_OUTP	(0x01 << 8)#define S3C2410_GPD4_VD12	(0x02 << 8)#define S3C2400_GPD4_LEND	(0x02 << 8)#define S3C2410_GPD5            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)#define S3C2410_GPD5_INP	(0x00 << 10)#define S3C2410_GPD5_OUTP	(0x01 << 10)#define S3C2410_GPD5_VD13	(0x02 << 10)#define S3C2400_GPD5_TOUT0	(0x02 << 10)#define S3C2410_GPD6            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)#define S3C2410_GPD6_INP	(0x00 << 12)#define S3C2410_GPD6_OUTP	(0x01 << 12)#define S3C2410_GPD6_VD14	(0x02 << 12)#define S3C2400_GPD6_TOUT1	(0x02 << 12)#define S3C2410_GPD7            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)#define S3C2410_GPD7_INP	(0x00 << 14)#define S3C2410_GPD7_OUTP	(0x01 << 14)#define S3C2410_GPD7_VD15	(0x02 << 14)#define S3C2400_GPD7_TOUT2	(0x02 << 14)#define S3C2410_GPD8            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)#define S3C2410_GPD8_INP	(0x00 << 16)#define S3C2410_GPD8_OUTP	(0x01 << 16)#define S3C2410_GPD8_VD16	(0x02 << 16)#define S3C2400_GPD8_TOUT3	(0x02 << 16)#define S3C2410_GPD9            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)#define S3C2410_GPD9_INP	(0x00 << 18)#define S3C2410_GPD9_OUTP	(0x01 << 18)#define S3C2410_GPD9_VD17	(0x02 << 18)#define S3C2400_GPD9_TCLK0	(0x02 << 18)#define S3C2410_GPD9_MASK       (0x03 << 18)#define S3C2410_GPD10           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)#define S3C2410_GPD10_INP	(0x00 << 20)#define S3C2410_GPD10_OUTP	(0x01 << 20)#define S3C2410_GPD10_VD18	(0x02 << 20)#define S3C2400_GPD10_nWAIT	(0x02 << 20)#define S3C2410_GPD11           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)#define S3C2410_GPD11_INP	(0x00 << 22)#define S3C2410_GPD11_OUTP	(0x01 << 22)#define S3C2410_GPD11_VD19	(0x02 << 22)#define S3C2410_GPD12           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)#define S3C2410_GPD12_INP	(0x00 << 24)#define S3C2410_GPD12_OUTP	(0x01 << 24)#define S3C2410_GPD12_VD20	(0x02 << 24)#define S3C2410_GPD13           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)#define S3C2410_GPD13_INP	(0x00 << 26)#define S3C2410_GPD13_OUTP	(0x01 << 26)#define S3C2410_GPD13_VD21	(0x02 << 26)#define S3C2410_GPD14           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)#define S3C2410_GPD14_INP	(0x00 << 28)#define S3C2410_GPD14_OUTP	(0x01 << 28)#define S3C2410_GPD14_VD22	(0x02 << 28)#define S3C2410_GPD15           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)#define S3C2410_GPD15_INP	(0x00 << 30)#define S3C2410_GPD15_OUTP	(0x01 << 30)#define S3C2410_GPD15_VD23	(0x02 << 30)#define S3C2410_GPD_PUPDIS(x)  (1<<(x))/* S3C2410: * Port E consists of 16 GPIO/Special function * * again, the same as port B, but dealing with I2S, SDI, and * more miscellaneous functions * * S3C2400: * Port E consists of 12 GPIO/Special function * * GPIO / interrupt inputs*/#define S3C2410_GPECON	   S3C2410_GPIOREG(0x40)#define S3C2410_GPEDAT	   S3C2410_GPIOREG(0x44)#define S3C2410_GPEUP	   S3C2410_GPIOREG(0x48)#define S3C2400_GPECON	   S3C2410_GPIOREG(0x2C)#define S3C2400_GPEDAT	   S3C2410_GPIOREG(0x30)#define S3C2400_GPEUP	   S3C2410_GPIOREG(0x34)#define S3C2410_GPE0           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)#define S3C2410_GPE0_INP       (0x00 << 0)#define S3C2410_GPE0_OUTP      (0x01 << 0)#define S3C2410_GPE0_I2SLRCK   (0x02 << 0)#define S3C2400_GPE0_EINT0     (0x02 << 0)#define S3C2410_GPE0_MASK      (0x03 << 0)#define S3C2410_GPE1           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)#define S3C2410_GPE1_INP       (0x00 << 2)#define S3C2410_GPE1_OUTP      (0x01 << 2)#define S3C2410_GPE1_I2SSCLK   (0x02 << 2)#define S3C2400_GPE1_EINT1     (0x02 << 2)#define S3C2400_GPE1_nSS       (0x03 << 2)#define S3C2410_GPE1_MASK      (0x03 << 2)#define S3C2410_GPE2           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)#define S3C2410_GPE2_INP       (0x00 << 4)#define S3C2410_GPE2_OUTP      (0x01 << 4)#define S3C2410_GPE2_CDCLK     (0x02 << 4)#define S3C2400_GPE2_EINT2     (0x02 << 4)#define S3C2400_GPE2_I2SSDI    (0x03 << 4)#define S3C2410_GPE3           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)#define S3C2410_GPE3_INP       (0x00 << 6)#define S3C2410_GPE3_OUTP      (0x01 << 6)#define S3C2410_GPE3_I2SSDI    (0x02 << 6)#define S3C2400_GPE3_EINT3     (0x02 << 6)#define S3C2400_GPE3_nCTS1     (0x03 << 6)#define S3C2410_GPE3_nSS0      (0x03 << 6)#define S3C2410_GPE3_MASK      (0x03 << 6)#define S3C2410_GPE4           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)#define S3C2410_GPE4_INP       (0x00 << 8)#define S3C2410_GPE4_OUTP      (0x01 << 8)#define S3C2410_GPE4_I2SSDO    (0x02 << 8)#define S3C2400_GPE4_EINT4     (0x02 << 8)#define S3C2400_GPE4_nRTS1     (0x03 << 8)#define S3C2410_GPE4_I2SSDI    (0x03 << 8)#define S3C2410_GPE4_MASK      (0x03 << 8)#define S3C2410_GPE5           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)#define S3C2410_GPE5_INP       (0x00 << 10)#define S3C2410_GPE5_OUTP      (0x01 << 10)#define S3C2410_GPE5_SDCLK     (0x02 << 10)#define S3C2400_GPE5_EINT5     (0x02 << 10)#define S3C2400_GPE5_TCLK1     (0x03 << 10)#define S3C2410_GPE6           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)#define S3C2410_GPE6_INP       (0x00 << 12)#define S3C2410_GPE6_OUTP      (0x01 << 12)#define S3C2410_GPE6_SDCMD     (0x02 << 12)#define S3C2400_GPE6_EINT6     (0x02 << 12)#define S3C2410_GPE7           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)#define S3C2410_GPE7_INP       (0x00 << 14)#define S3C2410_GPE7_OUTP      (0x01 << 14)#define S3C2410_GPE7_SDDAT0    (0x02 << 14)#define S3C2400_GPE7_EINT7     (0x02 << 14)#define S3C2410_GPE8           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)#define S3C2410_GPE8_INP       (0x00 << 16)#define S3C2410_GPE8_OUTP      (0x01 << 16)#define S3C2410_GPE8_SDDAT1    (0x02 << 16)#define S3C2400_GPE8_nXDACK0   (0x02 << 16)#define S3C2410_GPE9           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)#define S3C2410_GPE9_INP       (0x00 << 18)#define S3C2410_GPE9_OUTP      (0x01 << 18)#define S3C2410_GPE9_SDDAT2    (0x02 << 18)#define S3C2400_GPE9_nXDACK1   (0x02 << 18)#define S3C2400_GPE9_nXBACK    (0x03 << 18)#define S3C2410_GPE10          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)#define S3C2410_GPE10_INP      (0x00 << 20)#define S3C2410_GPE10_OUTP     (0x01 << 20)#define S3C2410_GPE10_SDDAT3   (0x02 << 20)#define S3C2400_GPE10_nXDREQ0  (0x02 << 20)#define S3C2410_GPE11          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)#define S3C2410_GPE11_INP      (0x00 << 22)#define S3C2410_GPE11_OUTP     (0x01 << 22)#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)#define S3C2400_GPE11_nXDREQ1  (0x02 << 22)#define S3C2400_GPE11_nXBREQ   (0x03 << 22)#define S3C2410_GPE12          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)#define S3C2410_GPE12_INP      (0x00 << 24)#define S3C2410_GPE12_OUTP     (0x01 << 24)#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)#define S3C2410_GPE13          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)#define S3C2410_GPE13_INP      (0x00 << 26)#define S3C2410_GPE13_OUTP     (0x01 << 26)#define S3C2410_GPE13_SPICLK0  (0x02 << 26)#define S3C2410_GPE14          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)#define S3C2410_GPE14_INP      (0x00 << 28)#define S3C2410_GPE14_OUTP     (0x01 << 28)#define S3C2410_GPE14_IICSCL   (0x02 << 28)#define S3C2410_GPE14_MASK     (0x03 << 28)#define S3C2410_GPE15          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)#define S3C2410_GPE15_INP      (0x00 << 30)#define S3C2410_GPE15_OUTP     (0x01 << 30)#define S3C2410_GPE15_IICSDA   (0x02 << 30)#define S3C2410_GPE15_MASK     (0x03 << 30)#define S3C2440_GPE0_ACSYNC    (0x03 << 0)#define S3C2440_GPE1_ACBITCLK  (0x03 << 2)#define S3C2440_GPE2_ACRESET   (0x03 << 4)#define S3C2440_GPE3_ACIN      (0x03 << 6)#define S3C2440_GPE4_ACOUT     (0x03 << 8)#define S3C2410_GPE_PUPDIS(x)  (1<<(x))/* S3C2410: * Port F consists of 8 GPIO/Special function * * GPIO / interrupt inputs * * GPFCON has 2 bits for each of the input pins on port F *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined * * pull up works like all other ports. * * S3C2400: * Port F consists of 7 GPIO/Special function * * GPIO/serial/misc pins*/#define S3C2410_GPFCON	   S3C2410_GPIOREG(0x50)#define S3C2410_GPFDAT	   S3C2410_GPIOREG(0x54)#define S3C2410_GPFUP	   S3C2410_GPIOREG(0x58)#define S3C2400_GPFCON	   S3C2410_GPIOREG(0x38)#define S3C2400_GPFDAT	   S3C2410_GPIOREG(0x3C)#define S3C2400_GPFUP	   S3C2410_GPIOREG(0x40)#define S3C2410_GPF0        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)#define S3C2410_GPF0_INP    (0x00 << 0)#define S3C2410_GPF0_OUTP   (0x01 << 0)#define S3C2410_GPF0_EINT0  (0x02 << 0)#define S3C2400_GPF0_RXD0   (0x02 << 0)#define S3C2410_GPF1        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)#define S3C2410_GPF1_INP    (0x00 << 2)#define S3C2410_GPF1_OUTP   (0x01 << 2)#define S3C2410_GPF1_EINT1  (0x02 << 2)#define S3C2400_GPF1_RXD1   (0x02 << 2)#define S3C2400_GPF1_IICSDA (0x03 << 2)#define S3C2410_GPF2        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)#define S3C2410_GPF2_INP    (0x00 << 4)#define S3C2410_GPF2_OUTP   (0x01 << 4)#define S3C2410_GPF2_EINT2  (0x02 << 4)#define S3C2400_GPF2_TXD0   (0x02 << 4)