/* qspanPci.h -  QSpan (QBus Controller) Header Module *//* Copyright 1998-2000 Wind River Systems, Inc. *//* Copyright 1997-2000 Motorola, Inc., All Rights Reserved *//*modification history--------------------01b,05dec00,rhk  WRS code standards cleanup.01a,27aug98,rhk  ported to CPV from MBX version 01f.*/#ifndef	INCqspanPcih#define	INCqspanPcih#ifdef __cplusplus    extern "C" {#endif /* __cplusplus *//* QSPAN register defines */#define QSPAN_PCI_ID		0x000 /* PCI cfg ID register */#define QSPAN_PCI_CS		0x004 /* PCI cfg control and status reg. */#define QSPAN_PCI_CLASS		0x008 /* PCI cfg class register */#define QSPAN_PCI_MISC0		0x00C /* PCI cfg miscellaneous 0 register */#define QSPAN_PCI_BSM		0x010 /* PCI cfg base addr for memory  */#define QSPAN_PCI_BSIO		0x014 /* PCI cfg base addr for I/O  */#define QSPAN_PCI_SID		0x02C /* PCI cfg subsystem ID register */#define QSPAN_PCI_BSROM		0x030 /* PCI cfg expansion ROM base addr */#define QSPAN_PCI_MISC1		0x03C /* PCI cfg misc 1 register */#define QSPAN_PBTI0_CTL		0x100 /* PCI target image 0 control */#define QSPAN_PBTI0_ADD		0x104 /* PCI target image 0 address */#define QSPAN_PBTI1_CTL		0x110 /* PCI target image 1 control */#define QSPAN_PBTI1_ADD		0x114 /* PCI target image 1 address */#define QSPAN_PBROM_CTL		0x13C /* PCI expansion ROM control */#define QSPAN_PB_ERRCS		0x140 /* PCI error control and status */#define QSPAN_PB_AERR		0x144 /* PCI bus address error log */#define QSPAN_PB_UERR		0x148 /* PCI bus data error log */#define QSPAN_IDMA_CS		0x400 /* IDMA control and status */#define QSPAN_IDMA_ADD		0x404 /* IDMA address */#define QSPAN_IDMA_CNT		0x408 /* IDMA transfer count */#define QSPAN_CON_ADD		0x500 /* configuration address */#define QSPAN_CON_DATA		0x504 /* configuration data */#define QSPAN_INT_STAT		0x600 /* interrupt status */#define QSPAN_INT_CTL		0x604 /* interrupt control */#define QSPAN_INT_DIR		0x608 /* interrupt direction control */#define QSPAN_MISC_CTL		0x800 /* miscellaneous control and status */#define QSPAN_QBSI0_CTL		0xF00 /* QBus slave image 0 control */#define QSPAN_QBSI0_AT		0xF04 /* QBus slave image 0 addr trans reg. */#define QSPAN_QBSI1_CTL		0xF10 /* QBus slave image 1 control */#define QSPAN_QBSI1_AT		0xF14 /* QBus slave image 1 addr trans reg. */#define QSPAN_QB_ERRCS		0xF80 /* QBus error log control and status */#define QSPAN_QB_AERR		0xF84 /* QBus address error log register */#define QSPAN_QB_DERR		0xF88 /* QBus data error log register *//* register settings used in the initialization of the QSPAN */#define QSPAN_DISABLE_REG	0x00000000 /* disables selected register */#define QSPAN_ENABLE_REG	0x00000001 /* enable the selected register */#define QSPAN_CLR_D_PE		0x80000000 /* clear detected parity error */#define QSPAN_CLR_S_SERR	0x40000000 /* clear signalled error */#define QSPAN_CLR_R_MA		0x20000000 /* clear receive master abort */#define QSPAN_CLR_R_TA		0x10000000 /* clear receive target abort */#define QSPAN_CLR_S_TA		0x08000000 /* clear signaled target abort */#define QSPAN_CLR_DP_D		0x01000000 /* clear data parity detect */#define QSPAN_ENABLE_BM		0x00000004 /* enable bus master */#define QSPAN_ENABLE_MS		0x00000002 /* enable memory space */#define QSPAN_ENABLE_IOS	0x00000001 /* enable IO space */#define QSPAN_MISC0_DISABLE_CACHELINE	0x00000000 /* CACHE line disabled */#define QSPAN_MISC0_CACHELINE_SIZE_4    0x00000004 /* 4x32-bit word cacheline */#define QSPAN_MISC0_CACHELINE_SIZE_8	0x00000008 /* 8x32-bit word cacheline */#define QSPAN_REV_ID_MASK	0x000000FF /* mask for the QSPAN revision ID */#define QSPAN_ENABLE_ERR_LOG	0x80000000 /* enable error logging */#define QSPAN_CLR_QES		0x01000000 /* clear QBUS error status *//* PCI space selection */#define QSPAN_PCI_MEM_SPACE	0x00000000 /* select PCI MEM space */#define QSPAN_PCI_IO_SPACE	0x00000001 /* select PCI I/O space *//* image defines */#define QSPAN_TARGET_IMAGE_0	0x00000000 /* select target image 0 */#define QSPAN_TARGET_IMAGE_1	0x00000001 /* select target image 1 */#define QSPAN_SLAVE_IMAGE_0	0x00000000 /* select slave image 0 */#define QSPAN_SLAVE_IMAGE_1	0x00000001 /* select slave image 1 */#define QSPAN_DISABLE_IMAGE	0x00000000 /* disable selected image */#define QSPAN_ENABLE_IMAGE	0x00000001 /* enable selected image *//* Slave image control bit fields */#define QSPAN_QBSI_MEM_SPACE	0x00000000 /* select PCI MEM space */#define QSPAN_QBSI_IO_SPACE	0x01000000 /* select PCI IO space */#define QSPAN_QBSI_PWEN		0x80000000 /* enable PCI write posting */#define QSPAN_QBSI_NO_PWEN	0x00000000 /* disable PCI write posting */#define QSPAN_QBSI_64KB		0x00000000 /* defines a 64KB block size */#define QSPAN_QBSI_128KB	0x00000010 /* defines a 128KB block size */#define QSPAN_QBSI_256KB	0x00000020 /* defines a 256KB block size */#define QSPAN_QBSI_512KB	0x00000030 /* defines a 512KB block size */#define QSPAN_QBSI_1MB		0x00000040 /* defines a 1MB block size */#define QSPAN_QBSI_2MB		0x00000050 /* defines a 2MB block size */#define QSPAN_QBSI_4MB		0x00000060 /* defines a 4MB block size */#define QSPAN_QBSI_8MB		0x00000070 /* defines a 8MB block size */#define QSPAN_QBSI_16MB		0x00000080 /* defines a 16MB block size */#define QSPAN_QBSI_32MB		0x00000090 /* defines a 32MB block size */#define QSPAN_QBSI_64MB		0x000000a0 /* defines a 64MB block size */#define QSPAN_QBSI_128MB	0x000000b0 /* defines a 128MB block size */#define QSPAN_QBSI_256MB	0x000000c0 /* defines a 256MB block size */#define QSPAN_QBSI_512MB	0x000000d0 /* defines a 512MB block size */#define QSPAN_QBSI_1GB		0x000000e0 /* defines a 1GB block size */#define QSPAN_QBSI_2GB		0x000000f0 /* defines a 2GB block size */#define QSPAN_QBSI_EN		0x00000001 /* enable the slave image *//* Target image control bit fields */#define QSPAN_QBTI_EN		0x80000000 /* enable the target image */#define QSPAN_QBTI_64KB         0x00000000 /* defines a 64KB block size */#define QSPAN_QBTI_128KB        0x01000000 /* defines a 128KB block size */#define QSPAN_QBTI_256KB        0x02000000 /* defines a 256KB block size */#define QSPAN_QBTI_512KB        0x03000000 /* defines a 512KB block size */#define QSPAN_QBTI_1MB          0x04000000 /* defines a MB block size */#define QSPAN_QBTI_2MB          0x05000000 /* defines a MB block size */#define QSPAN_QBTI_4MB          0x06000000 /* defines a MB block size */#define QSPAN_QBTI_8MB          0x07000000 /* defines a MB block size */#define QSPAN_QBTI_16MB         0x07000000 /* defines a MB block size */#define QSPAN_QBTI_32MB         0x09000000 /* defines a MB block size */#define QSPAN_QBTI_64MB         0x0a000000 /* defines a MB block size */#define QSPAN_QBTI_128MB        0x0b000000 /* defines a MB block size */#define QSPAN_QBTI_256MB        0x0c000000 /* defines a MB block size */#define QSPAN_QBTI_512MB        0x0d000000 /* defines a 512MB block size */#define QSPAN_QBTI_1GB          0x0e000000 /* defines a 1GB block size */#define QSPAN_QBTI_2GB          0x0f000000 /* defines a 2GB block size */#define QSPAN_QBTI_PREN		0x00800000 /* Prefetch read enable */#define QSPAN_QBTI_BRSTEN	0x00400000 /* Burst write enable */#define QSPAN_QBTI_INVEND	0x00080000 /* Invert endian-ness of QB_BOC */#define QSPAN_QBTI_PRT_SIZ32	0x00000000 /* port size = 32 bits */#define QSPAN_QBTI_PRT_SIZ16	0x00000800 /* port size = 16 bits */#define QSPAN_QBTI_PRT_SIZ8	0x00000400 /* port size = 8 bits */#define QSPAN_QBTI_PWEN         0x00000080 /* enable PCI write posting */#define QSPAN_QBTI_NO_PWEN      0x00000000 /* disable PCI write posting */#define QSPAN_QBTI_MEM_SPACE    0x00000000 /* select PCI MEM space */#define QSPAN_QBTI_IO_SPACE     0x00000040 /* select PCI IO space *//* Miscellaneous Control and Status Register bit settings */#define QSPAN_SET_S_BG		0x00080000 /* set synchronous bus grant */#define QSPAN_CLR_S_BG		0x00000000 /* clear synchronous bus grant */#define QSPAN_SET_S_BB		0x00040000 /* set synchronous BG acknowl. */#define QSPAN_CLR_S_BB		0x00000000 /* clear synchronous BG acknowl. */#define QSPAN_BOC_BE		0x00000000 /* use big-endian addressing */#define QSPAN_BOC_LE		0x00010000 /* use little-endian addressing */#define QSPAN_MA_BE_D		0x00001000 /* Bus error mapping disable */#define QSPAN_PRCNT_BITS	0x000000FC /* Prefetch read count bits */#define QSPAN_MSTSLV_0		0x00000000 /* MAST=QUICC, SLV=QUICC/68K */#define QSPAN_MSTSLV_1		0x00000001 /* MAST=QUICC, SLV=QUICC/PwrQUICC */#define QSPAN_MSTSLV_2		0x00000002 /* MAST=68K,   SLV=QUICC/68K */#define QSPAN_MSTSLV_3		0x00000003 /* MAST=PwrQUICC, SLV=QUICC/PwrQUICC */#define QSPAN_CLR_PEL_IS	0x80000000 /* PCI bus error log int. status */#define QSPAN_CLR_QEL_IS	0x40000000 /* QBus error log interrupt status */#define QSPAN_CLR_DPD_IS	0x20000000 /* data parity interrupt status */#define QSPAN_CLR_IPE_IS	0x08000000 /* IDMA PCI error interrupt status */#define QSPAN_CLR_IQE_IS	0x04000000 /* IDMA QBus error int. status */#define QSPAN_CLR_IRST_IS	0x02000000 /* IDMA reset interrupt status */#define QSPAN_CLR_DONE_IS	0x01000000 /* IDMA done interrupt status */#define QSPAN_CLR_SI1_IS	0x00000002 /* Software interrupt 1 status */#define QSPAN_CLR_SI0_IS	0x00000001 /* Software interrupt 0 status */#define QSPAN_CLR_IRST		0x00400000 /* clear the IDMA reset status */#define QSPAN_CLR_DONE		0x00200000 /* clear the IDMA Done status */#define QSPAN_CLR_IPE		0x00100000 /* clear the IDMA PCI error status */#define QSPAN_CLR_IQE		0x00080000 /* clear the IDMA Qbus err. status */#define QSPAN_SET_IMODE		0x00000008 /* set IDMA transfer for CPV *//* size in bytes of QSPAN register space */#define QSPAN_REG_SIZE	0x1000	/* 4KB register space */#ifdef __cplusplus    }#endif /* __cplusplus */#endif /* INCqspanPcih */