?? eep_040.lst
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C51 COMPILER V7.50 EEP_040 12/06/2006 11:04:37 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE EEP_040
OBJECT MODULE PLACED IN eep_040.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\c51.exe eep_040.c DB OE
line level source
1 /****************************************************************************
2 在主程序中有標識設斷點的地方，可觀察向鐵電存儲器寫入和讀取數據的情況
3 ****************************************************************************/
4 #include "C8051F040.h"
5
6 #define uchar unsigned char
7 #define uint unsigned int
8 #define WRITE 0x00 // WRITE direction bit
9 #define READ 0x01 // READ direction bit
10
11 #define CHIP_A 0xA0 // Device address for chip A
12 #define SMB_BUS_ERROR 0x00 // (all modes) BUS ERROR
13 #define SMB_START 0x08 // (MT & MR) START transmitted
14 #define SMB_RP_START 0x10 // (MT & MR) repeated START
15 #define SMB_MTADDACK 0x18 // (MT) Slave address + W transmitted;
16 // ACK received
17 #define SMB_MTADDNACK 0x20 // (MT) Slave address + W transmitted;
18 // NACK received
19 #define SMB_MTDBACK 0x28 // (MT) data byte transmitted; ACK rec'vd
20 #define SMB_MTDBNACK 0x30 // (MT) data byte transmitted; NACK rec'vd
21 #define SMB_MTARBLOST 0x38 // (MT) arbitration lost
22 #define SMB_MRADDACK 0x40 // (MR) Slave address + R transmitted;
23 // ACK received
24 #define SMB_MRADDNACK 0x48 // (MR) Slave address + R transmitted;
25 // NACK received
26 #define SMB_MRDBACK 0x50 // (MR) data byte rec'vd; ACK transmitted
27 #define SMB_MRDBNACK 0x58 // (MR) data byte rec'vd; NACK transmitted
28 uchar COMMAND; // Holds the slave address + R/W bit for
29 // use in the SMBus ISR.
30
31 uchar WORD; // Holds data to be transmitted by the SMBus
32 // OR data that has just been received.
33
34 uchar BYTE_NUMBER; // Used by ISR to check what data has just been
35 // sent - High address byte, Low byte, or data
36 // byte
37
38 uchar HIGH_ADD, LOW_ADD; // High & Low byte for EEPROM memory address
39
40 bit SM_BUSY;
41 void SMBus_ISR (void);
42 void SM_Send (uchar chip_select, uchar byte_address, uchar out_byte);
43 char SM_Receive (uchar chip_select, uchar byte_address);
44 void os_init();
45 void port_init();
46 void smbus_init();
47 void spi_init();
48 void uart_init();
49
50 void main()
51 {
52 1 uchar check;
53 1 WDTCN = 0xDE; // 關閉看門狗
54 1 WDTCN = 0xAD;
55 1 EIE1 = 0x02;
C51 COMPILER V7.50 EEP_040 12/06/2006 11:04:37 PAGE 2
56 1 EA=1;
57 1 os_init();
58 1 port_init();
59 1 spi_init();
60 1 uart_init();
61 1 smbus_init();
62 1 SM_BUSY=0;
63 1 while(1)
64 1 {
65 2 SM_Send(CHIP_A, 0x01, 0x55); // Send 0x53(data) to address 0x88 on CHIP_A
66 2
67 2
68 2 check = SM_Receive(CHIP_A, 0x01); // 在此處設斷點可觀察check值的變化
69 2
70 2 }
71 1
72 1 }
73 void os_init()
74 {
75 1 int i = 0;
76 1 SFRPAGE = CONFIG_PAGE;
77 1 OSCXCN = 0x67;
78 1 for (i = 0; i < 256; i++); // Wait 1ms for initialization
79 1 while ((OSCXCN & 0x80) == 0);
80 1 CLKSEL = 0x01;
81 1
82 1 }
83 void port_init()
84 {
85 1 SFRPAGE = CONFIG_PAGE;
86 1 XBR0 = 0x0f;
87 1 XBR2 = 0x40;
88 1 }
89
90 void spi_init()
91 {
92 1 SFRPAGE = SPI0_PAGE;
93 1 SPI0CFG = 0x40;
94 1 SPI0CN = 0x01;
95 1 SPI0CKR = 0x6D;
96 1
97 1
98 1 }
99 void uart_init()
100 {
101 1 SFRPAGE = UART0_PAGE;
102 1 SCON0 = 0x50; //允許uart1
103 1
104 1 }
105 void smbus_init()
106 {
107 1 SFRPAGE = SMB0_PAGE;
108 1 SMB0CN = 0x40; //允許ＳＭｂｕｓ
109 1 SMB0CR = 0x99; //系統(tǒng)時鐘為100KHZ
110 1
111 1 }
112
113 void SM_Send (uchar chip_select, uchar byte_address, uchar out_byte)
114 {
115 1 while (SM_BUSY); // Wait for SMBus to be free.
116 1 SM_BUSY = 1; // Occupy SMBus (set to busy)
117 1 SFRPAGE = SMB0_PAGE;
C51 COMPILER V7.50 EEP_040 12/06/2006 11:04:37 PAGE 3
118 1 SMB0CN = 0x44; // SMBus enabled,
119 1 // ACK on acknowledge cycle
120 1
121 1 BYTE_NUMBER = 2; // 2 address bytes.
122 1 COMMAND = (chip_select | WRITE); // Chip select + WRITE
123 1 LOW_ADD = (byte_address & 0xFF); // Lower 8 address bits
124 1
125 1 WORD = out_byte; // Data to be writen
126 1 SFRPAGE = SMB0_PAGE;
127 1 STO = 0;
128 1 STA = 1; // Start transfer
129 1
130 1 }
131
132 // SMBus random read function------------------------------------------------------
133 // Reads 1 byte from the specified memory location.
134 //
135 // byte_address = memory address of byte to read
136 // chip_select = device address of EEPROM to be read from
137 char SM_Receive (uchar chip_select, uchar byte_address)
138 {
139 1 while (SM_BUSY); // Wait for bus to be free.
140 1 SM_BUSY = 1; // Occupy SMBus (set to busy)
141 1 SFRPAGE = SMB0_PAGE;
142 1 SMB0CN = 0x44; // SMBus enabled, ACK on acknowledge cycle
143 1
144 1 BYTE_NUMBER = 2; // 2 address bytes
145 1 COMMAND = (chip_select | READ); // Chip select + READ
146 1 LOW_ADD = (byte_address & 0xFF); // Lower 8 address bits
147 1 SFRPAGE = SMB0_PAGE;
148 1 STO = 0;
149 1 STA = 1; // Start transfer
150 1 while (SM_BUSY); // Wait for transfer to finish
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