/*     adcm2650_hw - ADCM 2650 CMOS sensor driver    Copyright (C) 2003, Intel Corporation    This program is free software; you can redistribute it and/or modify    it under the terms of the GNU General Public License as published by    the Free Software Foundation; either version 2 of the License, or    (at your option) any later version.    This program is distributed in the hope that it will be useful,    but WITHOUT ANY WARRANTY; without even the implied warranty of    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    GNU General Public License for more details.    You should have received a copy of the GNU General Public License    along with this program; if not, write to the Free Software    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.*/#ifndef _ADCM_2650_HW_H_#define _ADCM_2650_HW_H_/*********************************************************************** * * Constants & Structures * ***********************************************************************/typedef struct {    u16 addr;    u16 value;} firm_update_t;typedef struct {    u16 width;    u16 height;} adcm_window_size;//ADCM_WINDOWSIZE;  // I2C address#define PIPE_SLAVE_ADDR     0x0052#define SENSOR_SLAVE_ADDR   0x0055// Revision constants#define PIPE_REV            0x0600#define SENSOR_REV          0x60// Calculating the Module Block Number#define BLOCK(a)            (u8)((a) >> 7)        // register's module block address.#define OFFSET(a)           (u8)((a) & 0x7F ) // register's offset to this block.// Return codes#define ADCM_ERR_NONE       0x00#define ADCM_ERR_TIMEOUT    -1#define ADCM_ERR_PARAMETER  -2  // Auto Exposure Frequency#define AEF_50HZ    0x20#define AEF_60HZ    0x40// Non JEPG Output Format#define O_FORMAT_888RGB         0   //0b0000    // 888 RGB (1 pixel in 3 bytes )#define O_FORMAT_666_A_RGB      1   //0b0001    // 666 A RGB (tight pack, 4 pixels in 9 bytes)#define O_FORMAT_666_B_RGB      2   //0b0010    // 666 B RGB (loose pack, 1 pixel in 3 bytes,left or right justified)#define O_FORMAT_565_RGB        3   //0b0011    // 565 RGB (1 pixel in 2 bytes)#define O_FORMAT_444_A_RGB      4   //0b0100    // 444 A RGB (tight pack, 2 pixels per 3 bytes, RG BR GB)#define O_FORMAT_444_B_RGB      5   //0b0101    // 444 B RGB (loose pack, 1 pixel per 2 bytes,RG B0 or 0R GB)#define O_FORMAT_444_C_RGV      6   //0b0110    // 444 C RGB (sparse pack, 1 pixel per three bytes,R0 G0 B0 or 0R 0G 0B)#define O_FORMAT_332_RGB        7   //0b0111    // 332 RGB (1 pixel in 1 byte)#define O_FORMAT_422_A_YCbYCr   8   //0b1000    // 4:2:2 A YCbYCr (Y1 Cb12 Y2 CRL2 order)#define O_FORMAT_422_B_YCbYCr   9   //0b1001    // 4:2:2 B YCbYCr (Cb12 Y1 CRL2 Y2 order)#define O_FORMAT_422_C_YCbYCr   10  //0b1010    // 4:2:2 C YCbYCr (Y1 CRL2 Y2 Cb12 order)#define O_FORMAT_422_D_YCbYCr   11  //0b1011    // 4:2:2 D YCbYCr (CRL2 Y1 Cb12 Y2 order)#define O_FORMAT_444_YCbYCr     12  //0b1100    // 4:4:4 YCbCr (1 pixels per 3 bytes)#define O_FORMAT_400_B_YCbYCr   13  //0b1101    // 4:0:0 YCbCr (Greyscale, 1 pixel per 1 byte)#define O_FORMAT_RAWBPA         14  //0b1110    // RAWBPA (with AWB and BPA)#define O_FORMAT_RAW            15  //0b1111    // RAW (without AWB and BPA)// Camera Mode#define VIEWFINDER_MODE     0x10#define STILLFRAME_MODE     0x20// Others#define adcm2650__TIMEOUT    1000    // ms to timeout.#define BLOCK_SWITCH_CMD    ((u8)0xFE)        // Block Switch Code: 0x7F, CMD = Code << 1#define CLOCK_13M   13#define VOLTS_28    0x28/*********************************************************************** * * Pipeline Register Offset * ***********************************************************************/// Image Processor Register List// Page 414#define REV             0x0000#define CMD_1           0x0002#define CMD_2           0x0004#define VIDEO_CONFIG    0x000c#define STILL_CONFIG    0x000e#define TM_SELECT       0x0010#define BYPASS_CTRL     0x0012#define PROCESS_CTRL    0x0014#define OUTPUT_CTRL     0x0016#define CCIR_TIMING_1   0x0018#define Y_MAX_MIN       0x001a#define CbCr_MAX_MIN    0x001c#define BAD_FRAME_DIS   0x001e#define UART_PCKT_SIZE  0x0020#define UART_CRDT_ADD   0x0022#define UART_CREDITS    0x0024#define SZR_IN_W_VID    0x0026  #define SZR_IN_H_VID    0x0028  #define SZR_OUT_W_VID   0x002a  #define SZR_OUT_H_VID   0x002c  #define SZR_IN_W_STL    0x002e  #define SZR_IN_H_STL    0x0030  #define SZR_OUT_W_STL   0x0032  #define SZR_OUT_H_STL   0x0034  #define QTABLE_SELECT   0x0036// Page 415#define QTABLE_MAX_MIN  0x0038#define UFL_LIMIT_VID   0x003a#define UFL_TARGET_VID  0x003c#define OFL_TARGET_VID  0x003e#define OFL_LIMIT_VID   0x0040#define UFL_LIMIT_STL   0x0042#define UFL_TARGET_STL  0x0044#define OFL_TARGET_STL  0x0046#define OFL_LIMIT_STL   0x0048#define SENSOR_ADDRESS  0x004a#define SENSOR_DATA_1   0x004c#define SENSOR_DATA_2   0x004e#define SENSOR_CTRL     0x0050#define PLL_CTRL_0      0x0052#define PLL_CTRL_1      0x0054#define PLL_CTRL_2      0x0056#define DIVBY_UART      0x0058#define EXT_DIVBY_VID   0x005a#define EXT_DIVBY_STL   0x005c#define STAT_CAP_CTRL   0x005e#define STAT_MODE_CTRL  0x0060#define GREEN1_SUM      0x0062#define READ_SUM        0x0064#define BLUE_SUM        0x0066#define GREEN2_SUM      0x0068#define NEG_CLIP_CNT    0x006a#define POS_CLIP_CNT    0x006c#define PEAK_DATA       0x006e#define I_WIDTH         0x0070#define I_HEIGHT        0x0072// Page 416#define STATUS_FLAGS    0x0074#define STATUS_REG      0x0076#define PLL_DIVBY_VID   0x0078#define PLL_DIVBY_STL   0x007a#define OUTPUT_CTRL_2   0x007c#define CC_COEF_00      0x0080#define CC_COEF_01      0x0082#define CC_COEF_02      0x0084#define CC_COEF_10      0x0086#define CC_COEF_11      0x0088#define CC_COEF_12      0x008a#define CC_COEF_20      0x008c#define CC_COEF_21      0x008e#define CC_COEF_22      0x0090#define CC_OS_0         0x0092#define CC_OS_1         0x0094#define CC_OS_2         0x0096#define CSC_COEF_00V    0x0098#define CSC_COEF_01V    0x009a#define CSC_COEF_02V    0x009c#define CSC_COEF_10V    0x009e#define CSC_COEF_11V    0x00a0#define CSC_COEF_12V    0x00a2#define CSC_COEF_20V    0x00a4#define CSC_COEF_21V    0x00a6#define CSC_COEF_22V    0x00a8#define CSC_OS_0V       0x00aa#define CSC_OS_1V       0x00ac#define CSC_OS_2V       0x00ae// Page 417#define CSC_COEF_00S    0x00b0#define CSC_COEF_01S    0x00b2#define CSC_COEF_02S    0x00b4#define CSC_COEF_10S    0x00b6#define CSC_COEF_11S    0x00b8#define CSC_COEF_12S    0x00ba#define CSC_COEF_20S    0x00bc#define CSC_COEF_21S    0x00be#define CSC_COEF_22S    0x00c0#define CSC_OS_0S       0x00c2#define CSC_OS_1S       0x00c4#define CSC_OS_2S       0x00c6#define APS_COEF_GRN1   0x0100#define APS_COEF_RED    0x0102#define APS_COEF_BLUE   0x0104#define APS_COEF_GRN2   0x0106#define T_DGEN_M        0x0108#define CCIR_TIMING_2   0x010a#define CCIR_TIMING_3   0x010c#define SERIAL_CTRL     0x010e#define DM_COEF_GRN1    0x0110#define DM_COEF_RED     0x0112#define DM_COEF_BLUE    0x0114#define DM_COEF_GRN2    0x0116#define SSC_TIMING      0x0118#define SSC_PERIOD      0x011a#define JPEG_RESTART    0x011c// Page 418#define HSYNC_PER_VID   0x011e#define HSYNC_PER_STL   0x0120#define G1_G2_THRESH    0x0124#define S_PLL_CTRL_0    0x0126#define S_PLL_CTRL_1    0x0128#define S_PLL_CTRL_2    0x012a#define S_DIVBY_UART    0x012c#define S_EXT_DIVBY_VID 0x012e#define S_EXT_DIVBY_STL 0x0130#define BAD_FRAME_CNT_1 0x0132#define BAD_FRAME_CNT_2 0x0134#define BAD_FRAME_CNT_3 0x0136#define BAD_FRAME_CNT_4 0x0138#define OUT_FRAME_CNT   0x013a#define DROP_FRAME_CNT  0x013c#define BPA_BADPIX_CNT  0x013e#define APS_FRAME_CNT   0x0140#define BPA_OUTL_PED    0x0142#define BPA_SCALE       0x0144#define S_PLL_DIVBY_VID 0x0146