?? startup.s
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;/****************************************Copyright (c)**************************************************
;** Guangzhou ZHIYUAN electronics Co.,LTD.
;**
;** http://www.zyinside.com
;**
;**--------------File Info-------------------------------------------------------------------------------
;** File Name: startup.s
;** Last modified Date: 2006-01-06
;** Last Version: v1.1
;** Descriptions: S3C2410異常向量入口及異常向量與c語言代碼的接口，包括初始化堆棧、初始化PLL的代碼
;**
;**------------------------------------------------------------------------------------------------------
;** Created By: 黃紹斌
;** Created date: 2005-11-11
;** Version: v1.0
;** Descriptions: 創(chuàng)建
;**
;**------------------------------------------------------------------------------------------------------
;** Modified by: 甘達
;** Modified date: 2006-01-06
;** Version: v1.1
;** Descriptions:
;**
;**------------------------------------------------------------------------------------------------------
;** Modified by:
;** Modified date:
;** Version:
;** Descriptions:
;**
;********************************************************************************************************/
IMPORT __use_no_semihosting_swi
; /* 定義堆棧的大小 */
; **** 用戶可根據(jù)實際需要修改 ****
SVC_STACK_LEGTH EQU 16
FIQ_STACK_LEGTH EQU 16
IRQ_STACK_LEGTH EQU 9*8
ABT_STACK_LEGTH EQU 0
UND_STACK_LEGTH EQU 0
; /*************************************************************************/
; /* CPSR寄存器的位域 */
; /*************************************************************************/
; /* */
; /* 31 30 29 28 7 6 5 4 3 2 1 0 */
; /*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */
; /*| N | Z | C | V | | I | F | T | M4 ~ M0 | */
; /*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */
; /* */
; /* Processor Mode and Mask */
; /* */
; /*************************************************************************/
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_BIT EQU 0x80 ; when I bit is set (1), IRQ is disabled
F_BIT EQU 0x40 ; when F bit is set (1), FIQ is disabled
; 總線寬度控制定義(0表示8位，1表示16位，2表示32位)
DW8 EQU (0x0)
DW16 EQU (0x1)
DW32 EQU (0x2)
WAIT EQU (0x1<<2)
UBLB EQU (0x1<<3)
; **** 用戶可根據(jù)實際需要修改 ****
B7_BWCON EQU (DW16|WAIT|UBLB)
B6_BWCON EQU (DW32|UBLB)
B5_BWCON EQU (DW16|WAIT|UBLB)
B4_BWCON EQU (DW16|WAIT|UBLB)
B3_BWCON EQU (DW16|WAIT|UBLB)
B2_BWCON EQU (DW16|WAIT|UBLB)
B1_BWCON EQU (DW16|WAIT|UBLB)
; CPU時鐘設置(PLLCON控制值)
; 50.00MHz (外部晶振為12MHz時)
MDIV_50 EQU 0x5C
PDIV_50 EQU 0x4
SDIV_50 EQU 0x2
; 200.00MHz (外部晶振為12MHz時)
; 設置值為：m=100,p=6,s=0, MPLL=FCLK=12*100/6=200MHz
MDIV_200 EQU 0x5C
PDIV_200 EQU 0x4
SDIV_200 EQU 0x0
MPLLCON_200 EQU ((MDIV_200 << 12) | (PDIV_200 << 4) | (SDIV_200))
; 寄存器定義
;=================
; WATCH DOG TIMER
;=================
WTCON EQU 0x53000000 ;Watch-dog timer mode
WTDAT EQU 0x53000004 ;Watch-dog timer data
WTCNT EQU 0x53000008 ;Eatch-dog timer count
;=================
; INTERRUPT
;=================
SRCPND EQU 0x4a000000 ;Interrupt request status
INTMOD EQU 0x4a000004 ;Interrupt mode control
INTMSK EQU 0x4a000008 ;Interrupt mask control
PRIORITY EQU 0x4a00000c ;IRQ priority control
INTPND EQU 0x4a000010 ;Interrupt request status
INTOFFSET EQU 0x4a000014 ;Interruot request source offset
SUSSRCPND EQU 0x4a000018 ;Sub source pending
INTSUBMSK EQU 0x4a00001c ;Interrupt sub mask
;=================
; Memory control
;=================
BWSCON EQU 0x48000000 ;Bus width & wait status
BANKCON0 EQU 0x48000004 ;Boot ROM control
BANKCON1 EQU 0x48000008 ;BANK1 control
BANKCON2 EQU 0x4800000c ;BANK2 cControl
BANKCON3 EQU 0x48000010 ;BANK3 control
BANKCON4 EQU 0x48000014 ;BANK4 control
BANKCON5 EQU 0x48000018 ;BANK5 control
BANKCON6 EQU 0x4800001c ;BANK6 control
BANKCON7 EQU 0x48000020 ;BANK7 control
REFRESH EQU 0x48000024 ;DRAM/SDRAM refresh
BANKSIZE EQU 0x48000028 ;Flexible Bank Size
MRSRB6 EQU 0x4800002c ;Mode register set for SDRAM
MRSRB7 EQU 0x48000030 ;Mode register set for SDRAM
;==========================
; CLOCK & POWER MANAGEMENT
;==========================
LOCKTIME EQU 0x4c000000 ;PLL lock time counter
MPLLCON EQU 0x4c000004 ;MPLL Control
UPLLCON EQU 0x4c000008 ;UPLL Control
CLKCON EQU 0x4c00000c ;Clock generator control
CLKSLOW EQU 0x4c000010 ;Slow clock control
CLKDIVN EQU 0x4c000014 ;Clock divider control
; /************************************************************************/
; 引入的外部標號在這聲明
IMPORT __main ;C語言主程序入口
IMPORT SoftwareInterrupt
; 給外部使用的標號在這聲明
EXPORT Reset
EXPORT VICVectAddr
EXPORT bottom_of_heap
EXPORT StackUsr
EXPORT __user_initial_stackheap
; /************************************************************************/
CODE32
AREA vectors,CODE,READONLY
; 異常向量表
Reset
LDR PC, ResetAddr
LDR PC, UndefinedAddr
LDR PC, SWI_Addr
LDR PC, PrefetchAddr
LDR PC, DataAbortAddr
DCD IRQ_Addr
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
ResetAddr DCD ResetInit
UndefinedAddr DCD Undefined
SWI_Addr DCD SoftwareInterrupt
PrefetchAddr DCD PrefetchAbort
DataAbortAddr DCD DataAbort
Nouse DCD 0
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
; 未定義指令
Undefined
B Undefined
SwiFunction
DCD IRQDisable ;0
DCD IRQEnable ;1
DCD FIQDisable ;2
DCD FIQEnable ;3
IRQDisable
;關(guān)IRQ中斷
MRS R0, SPSR
ORR R0, R0, #I_BIT
MSR SPSR_c, R0
MOVS PC, LR
IRQEnable
;開IRQ中斷
MRS R0, SPSR
BIC R0, R0, #I_BIT
MSR SPSR_c, R0
MOVS PC, LR
FIQDisable
;關(guān)FIQ中斷
MRS R0, SPSR
ORR R0, R0, #F_BIT
MSR SPSR_c, R0
MOVS PC, LR
FIQEnable
;開FIQ中斷
MRS R0, SPSR
BIC R0, R0, #F_BIT
MSR SPSR_c, R0
MOVS PC, LR
; 取指中止
PrefetchAbort
B PrefetchAbort
; 取數(shù)據(jù)中止
DataAbort
B DataAbort
; IRQ中斷
NoInt EQU 0x80
USR32Mode EQU 0x10
SVC32Mode EQU 0x13
SYS32Mode EQU 0x1f
IRQ32Mode EQU 0x12
FIQ32Mode EQU 0x11
;引入的外部標號在這聲明
IMPORT OSIntCtxSw ;任務切換函數(shù)
IMPORT OSIntExit ;中斷退出函數(shù)
IMPORT OSTCBCur
IMPORT OSTCBHighRdy
IMPORT OSIntNesting ;中斷嵌套計數(shù)器
IMPORT OsEnterSum
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