?? mpgiface.h
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/*******************************************************************************
File Name : mpgiface.h
Description : This header file contains the video, audio, denc registers
definitions of STi5500, with the macros (read/write) to access
them
(C)Copyright ST Microelectronics 1998
Reference to the origin of this file within the clearcase repository
\5500ref\mpeg\mpgiface.h
References to related design specifications, tools, required header files etc.
Revision History (Latest modification on top) :
Date Modification Initials
---- ------------ --------
16-Sep-98 Removed VIDEO_DCF_FLD and VIDEO_DCF_USR constants PL
14-Aug-98 Added VIDEO_PPR1_OTF and VIDEO_TRF_TRF constants PL
22-Jul-98 * Nb of wait states on mpeg reg accesses depends on
the STi5500 version (5 for version A and B, 2 for
version C, D , and later)
* Added Denc registers definition missed for
STI5500_VERSION_A PL
26-Jun-98 Rewrote mpeg registers read/write macros LD
19-Jun-98 decrease nb of wait states on mpeg reg accesses LD
28-Oct-97 Placed sdram map in mpeg.h LD
05-Sep-97 Added Display Mode selection constants THT
14-Nov-96 Added DXX DENC registers LD
15-Oct-96 Modified erroneous register PG
11-Sep-96 Added DXX specific registers YK
26-Apr-96 Swapped vide/audio interrupt address JMW
18-May-95 Created NH
*******************************************************************************/
/* Define to prevent recursive inclusion */
#ifndef _MPGIFACE_H_
#define _MPGIFACE_H_
/* Includes ----------------------------------------------------------------- */
/*
#include "mpeg.h"
*/
/* Exported Types ----------------------------------------------------------- */
/* Exported Constants ------------------------------------------------------- */
#define PAL_MODE 0
#define NTSC_MODE 1
/* default vbv_delay value for any PAL/ NTSC streams */
#define MAX_VBV_ALLOWED 0x380
/* -------------------------------------
Here we have the DMA registers
------------------------------------- */
#define MPEG_VIDEO_DMA_BURSTSIZE 0x20020000
#define MPEG_VIDEO_DMA_HOLDOFF 0x20020004
#define MPEG_VIDEO_DMA_SUSPEND 0x20020008
#define MPEG_VIDEO_DMA_SELECT 0x2002000C
#define MPEG_AUDIO_DMA_BURSTSIZE 0x20021000
#define MPEG_AUDIO_DMA_HOLDOFF 0x20021004
#define MPEG_AUDIO_DMA_SUSPEND 0x20021008
#define MPEG_AUDIO_DMA_SELECT 0x2002100C
/* -------------------------------------
Here we have the values of the XDO
XDS YDO and YDS registers
------------------------------------- */
#define VIDEO_DISPLAY_SIZE_N 720
#define VIDEO_DISPLAY_HEIGHT_N 480
#define DISPLAY_XDO_N 0x64
#define DISPLAY_XDS_N (DISPLAY_XDO_N + VIDEO_DISPLAY_SIZE_N + 6)
#define DISPLAY_YDO_N 0x13
#define DISPLAY_YDS_N 0x82
#define VIDEO_DISPLAY_SIZE_P 720
#define VIDEO_DISPLAY_HEIGHT_P 576
#define DISPLAY_XDO_P 0x6c
#define DISPLAY_XDS_P (DISPLAY_XDO_P + VIDEO_DISPLAY_SIZE_P + 6)
#define DISPLAY_YDO_P 0x16
#define DISPLAY_YDS_P 0xB5
/* -------------------------------------
Registers map in the uc memory space
------------------------------------- */
#define MPEG_VIDEO_REG2WS_MIN_ADD 0x1000
#define MPEG_VIDEO_REG3WS_MIN_ADD 0x1080
#define MPEG_VIDEO_REG4WS_MIN_ADD 0x1100
#define MPEG_VIDEO_REG5WS_MIN_ADD 0x1180
#define MPEG_AUDIO_REG2WS_MIN_ADD 0x1200
#define MPEG_AUDIO_REG3WS_MIN_ADD 0x1280
#define MPEG_AUDIO_REG4WS_MIN_ADD 0x1300
#define MPEG_AUDIO_REG5WS_MIN_ADD 0x1380
#define MPEG_DENC_REG2WS_MIN_ADD 0x1600
#define MPEG_DENC_REG3WS_MIN_ADD 0x1680
#define MPEG_DENC_REG4WS_MIN_ADD 0x1700
#define MPEG_DENC_REG5WS_MIN_ADD 0x1780
#define MPEG_SPC_REG2WS_MIN_ADD 0x1400
#define MPEG_SPC_REG3WS_MIN_ADD 0x1480
#define MPEG_SPC_REG4WS_MIN_ADD 0x1500
#define MPEG_SPC_REG5WS_MIN_ADD 0x1580
#define VIDEO_REGISTERS_BASE 0
#define AUDIO_REGISTERS_BASE 0x200
#define DENC_REGISTERS_BASE 0x600
#define SPC_REGISTERS_BASE VIDEO_REGISTERS_BASE
/* Register Address Map */
/* MPEG registers */
#define CFG_MCF (VIDEO_REGISTERS_BASE + 0x00)
#define CFG_CCF (VIDEO_REGISTERS_BASE + 0x01)
#define VID_CTL (VIDEO_REGISTERS_BASE + 0x02)
#define VID_TIS (VIDEO_REGISTERS_BASE + 0x03)
#define VID_PFH (VIDEO_REGISTERS_BASE + 0x04)
#define VID_PFV (VIDEO_REGISTERS_BASE + 0x05)
#define VID_PPR1 (VIDEO_REGISTERS_BASE + 0x06)
#define VID_PPR2 (VIDEO_REGISTERS_BASE + 0x07)
#define CFG_BMS (VIDEO_REGISTERS_BASE + 0x09)
#define CFG_MRP (VIDEO_REGISTERS_BASE + 0x0A)
#define CFG_MWP (VIDEO_REGISTERS_BASE + 0x0B)
#define VID_MRP CFG_MRP
#define VID_MWP CFG_MWP
#define VID_DFP (VIDEO_REGISTERS_BASE + 0x0C) /* 14 bit reg */
#define VID_RFP (VIDEO_REGISTERS_BASE + 0x0E) /* 14 bit reg */
#define VID_FFP (VIDEO_REGISTERS_BASE + 0x10) /* 14 bit reg */
#define VID_BFP (VIDEO_REGISTERS_BASE + 0x12) /* 14 bit reg */
#define VID_VBG (VIDEO_REGISTERS_BASE + 0x14) /* 14 bit reg */
#define VID_VBL (VIDEO_REGISTERS_BASE + 0x16) /* 14 bit reg */
#define VID_VBS (VIDEO_REGISTERS_BASE + 0x18) /* 14 bit reg */
#define VID_VBT (VIDEO_REGISTERS_BASE + 0x1A) /* 14 bit reg */
#define VID_ABG (VIDEO_REGISTERS_BASE + 0x1C) /* 14 bit reg */
#define VID_ABL (VIDEO_REGISTERS_BASE + 0x1E) /* 14 bit reg */
#define VID_ABS (VIDEO_REGISTERS_BASE + 0x20) /* 14 bit reg */
#define VID_ABT (VIDEO_REGISTERS_BASE + 0x22) /* 14 bit reg */
#define VID_DFS (VIDEO_REGISTERS_BASE + 0x24)
#define VID_DFW (VIDEO_REGISTERS_BASE + 0x25)
#define VID_XFW (VIDEO_REGISTERS_BASE + 0x28)
#define VID_OTP (VIDEO_REGISTERS_BASE + 0x2A)
#define VID_OBP (VIDEO_REGISTERS_BASE + 0x2B)
#define VID_SM (VIDEO_REGISTERS_BASE + 0x2C) /* 12 bit reg */
#define VID_PTH (VIDEO_REGISTERS_BASE + 0x2E)
#define CKG_PLL (VIDEO_REGISTERS_BASE + 0x30)
#define CKG_CFG (VIDEO_REGISTERS_BASE + 0x31)
#define CKG_SMC (VIDEO_REGISTERS_BASE + 0x32)
#define CKG_LNK (VIDEO_REGISTERS_BASE + 0x33)
#define CKG_PIX (VIDEO_REGISTERS_BASE + 0x34)
#define CKG_PCM (VIDEO_REGISTERS_BASE + 0x35)
#define CKG_MCK (VIDEO_REGISTERS_BASE + 0x36)
#define CKG_AUX (VIDEO_REGISTERS_BASE + 0x37)
#define CFG_DRCF (VIDEO_REGISTERS_BASE + 0x38)
#define CFG_GCF (VIDEO_REGISTERS_BASE + 0x3A)
#define VID_STA_HIGH (VIDEO_REGISTERS_BASE + 0x3B) /* VID_STA [23:16] */
#define VID_ITM_HIGH (VIDEO_REGISTERS_BASE + 0x3C) /* VID_ITM [23:16] */
#define VID_ITS_HIGH (VIDEO_REGISTERS_BASE + 0x3D) /* VID_ITS [23:16] */
#define VID_OSD (VIDEO_REGISTERS_BASE + 0x3E)
#define VID_LDP (VIDEO_REGISTERS_BASE + 0x3F)
#define PES_CF1 (VIDEO_REGISTERS_BASE + 0x40)
#define PES_CF2 (VIDEO_REGISTERS_BASE + 0x41)
#define PES_TM1 (VIDEO_REGISTERS_BASE + 0x42)
#define PES_TM2 (VIDEO_REGISTERS_BASE + 0x43)
#define CFG_CDR (VIDEO_REGISTERS_BASE + 0x44)
#define VID_FRZ (VIDEO_REGISTERS_BASE + 0x45)
#define PES_SC1 (VIDEO_REGISTERS_BASE + 0x44)
#define PES_SC2 (VIDEO_REGISTERS_BASE + 0x45)
#define PES_SC3 (VIDEO_REGISTERS_BASE + 0x46)
#define PES_SC4 (VIDEO_REGISTERS_BASE + 0x47)
#define PES_SC5 (VIDEO_REGISTERS_BASE + 0x48)
#define PES_TS1 (VIDEO_REGISTERS_BASE + 0x49)
#define PES_TS2 (VIDEO_REGISTERS_BASE + 0x4A)
#define PES_TS3 (VIDEO_REGISTERS_BASE + 0x4B)
#define PES_TS4 (VIDEO_REGISTERS_BASE + 0x4C)
#define PES_TS5 (VIDEO_REGISTERS_BASE + 0x4D)
#define VID_SPRead (VIDEO_REGISTERS_BASE + 0x4E)
#define VID_SPWrite (VIDEO_REGISTERS_BASE + 0x4F)
#define VID_SPB (VIDEO_REGISTERS_BASE + 0x50)
#define VID_SPE (VIDEO_REGISTERS_BASE + 0x52)
#define VID_MLU (VIDEO_REGISTERS_BASE + 0x54)
#define VID_MCH (VIDEO_REGISTERS_BASE + 0x55)
#define VID_TRF (VIDEO_REGISTERS_BASE + 0x56)
#define VID_DFC (VIDEO_REGISTERS_BASE + 0x58)
#define VID_RFC (VIDEO_REGISTERS_BASE + 0x5A)
#define VID_FFC (VIDEO_REGISTERS_BASE + 0x5C)
#define VID_BFC (VIDEO_REGISTERS_BASE + 0x5E)
#define VID_ITM (VIDEO_REGISTERS_BASE + 0x60) /* 16 BIT REG */
#define VID_ITS (VIDEO_REGISTERS_BASE + 0x62) /* 16 BIT REG */
#define VID_STA (VIDEO_REGISTERS_BASE + 0x64) /* 16 BIT REG */
#define VID_HDF (VIDEO_REGISTERS_BASE + 0x66)
#define VID_CD_COUNT (VIDEO_REGISTERS_BASE + 0x67)
#define VID_SCD_COUNT (VIDEO_REGISTERS_BASE + 0x68)
#define VID_HDS (VIDEO_REGISTERS_BASE + 0x69)
#define VID_LSO (VIDEO_REGISTERS_BASE + 0x6A)
#define VID_LSR (VIDEO_REGISTERS_BASE + 0x6B) /* LSR [7:0] */
#define VID_CSO (VIDEO_REGISTERS_BASE + 0x6C)
#define VID_LSR_HIGH (VIDEO_REGISTERS_BASE + 0x6D) /* 2 bit reg LSR [8] & BS */
#define VID_YDO (VIDEO_REGISTERS_BASE + 0x6E)
#define VID_YDS (VIDEO_REGISTERS_BASE + 0x6F)
#define VID_XDO (VIDEO_REGISTERS_BASE + 0x70) /* 10 BIT REG XDO [9:0] */
#define VID_XDS (VIDEO_REGISTERS_BASE + 0x72) /* 10 BIT REG XDS [9:0] */
#define VID_DCF (VIDEO_REGISTERS_BASE + 0x74) /* 16 BIT REG DCF [15:0] */
#define VID_QMW (VIDEO_REGISTERS_BASE + 0x76)
#define VID_TST (VIDEO_REGISTERS_BASE + 0x77)
#define VID_REV (VIDEO_REGISTERS_BASE + 0x78)
#define VID_DC2 (VIDEO_REGISTERS_BASE + 0x79)
/* DENC registers */
#define DENC_CFG0 (DENC_REGISTERS_BASE + 00) /* default: 8 bit regs */
#define DENC_CFG1 (DENC_REGISTERS_BASE + 01)
#define DENC_CFG2 (DENC_REGISTERS_BASE + 02)
#define DENC_CFG3 (DENC_REGISTERS_BASE + 03)
#define DENC_CFG4 (DENC_REGISTERS_BASE + 04)
#define DENC_CFG5 (DENC_REGISTERS_BASE + 05) /* 7 bits xvvv vvvv */
#ifdef STI5500_VERSION_A
#define DENC_IDFS0 (DENC_REGISTERS_BASE + 10) /* Increment DFS registers */
#define DENC_IDFS1 (DENC_REGISTERS_BASE + 11)
#define DENC_IDFS2 (DENC_REGISTERS_BASE + 12)
#define DENC_PDFS0 (DENC_REGISTERS_BASE + 13)
#define DENC_PDFS1 (DENC_REGISTERS_BASE + 14)
#define DENC_PDFS2 (DENC_REGISTERS_BASE + 15) /* Phase offset for Digit
Freq Synth */
#define DENC_LINEREG0 (DENC_REGISTERS_BASE + 21)
#define DENC_LINEREG1 (DENC_REGISTERS_BASE + 22)
#define DENC_LINEREG2 (DENC_REGISTERS_BASE + 23)
#define DENC_TTXBLOC1 (DENC_REGISTERS_BASE + 34)
#define DENC_TTXBLOC2 (DENC_REGISTERS_BASE + 35)
#define DENC_TTXBLOC3 (DENC_REGISTERS_BASE + 36)
#define DENC_TTXBLOC4 (DENC_REGISTERS_BASE + 37)
#define DENC_TTXBMAP (DENC_REGISTERS_BASE + 38)
#define DENC_CCCF11 (DENC_REGISTERS_BASE + 39)
#define DENC_CCCF12 (DENC_REGISTERS_BASE + 40)
#define DENC_CCCF21 (DENC_REGISTERS_BASE + 41)
#define DENC_CCCF22 (DENC_REGISTERS_BASE + 42)
#define DENC_CCLIF1 (DENC_REGISTERS_BASE + 43)
#define DENC_CCLIF2 (DENC_REGISTERS_BASE + 44)
#define DENC_R45 (DENC_REGISTERS_BASE + 45)
#define DENC_CHIPID (DENC_REGISTERS_BASE + 61)
#define DENC_REVID (DENC_REGISTERS_BASE + 62)
#define DENC_STS (DENC_REGISTERS_BASE + 63) /* status; READ ONLY */
#else
#define DENC_CFG6 (DENC_REGISTERS_BASE + 06) /* 7 bits vvvv vvxv */
#define DENC_STS (DENC_REGISTERS_BASE + 09) /* status; READ ONLY */
#define DENC_IDFS0 (DENC_REGISTERS_BASE + 10) /* Increment DFS registers */
#define DENC_IDFS1 (DENC_REGISTERS_BASE + 11)
#define DENC_IDFS2 (DENC_REGISTERS_BASE + 12)
#define DENC_PDFS0 (DENC_REGISTERS_BASE + 13)
#define DENC_PDFS1 (DENC_REGISTERS_BASE + 14) /* Phase offset for Digit Freq Synth */
#define DENC_CHIPID (DENC_REGISTERS_BASE + 17)
#define DENC_REVID (DENC_REGISTERS_BASE + 18)
#define DENC_LINEREG0 (DENC_REGISTERS_BASE + 21)
#define DENC_LINEREG1 (DENC_REGISTERS_BASE + 22)
#define DENC_LINEREG2 (DENC_REGISTERS_BASE + 23)
#define DENC_CGMS0 (DENC_REGISTERS_BASE + 31)
#define DENC_CGMS1 (DENC_REGISTERS_BASE + 32)
#define DENC_CGMS2 (DENC_REGISTERS_BASE + 33)
#define DENC_TTXBLOC1 (DENC_REGISTERS_BASE + 34)
#define DENC_TTXBLOC2 (DENC_REGISTERS_BASE + 35)
#define DENC_TTXBLOC3 (DENC_REGISTERS_BASE + 36)
#define DENC_TTXBLOC4 (DENC_REGISTERS_BASE + 37)
#define DENC_TTXBMAP (DENC_REGISTERS_BASE + 38)
#define DENC_CCCF11 (DENC_REGISTERS_BASE + 39)
#define DENC_CCCF12 (DENC_REGISTERS_BASE + 40)
#define DENC_CCCF21 (DENC_REGISTERS_BASE + 41)
#define DENC_CCCF22 (DENC_REGISTERS_BASE + 42)
#define DENC_CCLIF1 (DENC_REGISTERS_BASE + 43)
#define DENC_CCLIF2 (DENC_REGISTERS_BASE + 44)
#define DENC_R45 (DENC_REGISTERS_BASE + 45)
#endif
/* SubPicture registers */
#define SP_CTL1 (SPC_REGISTERS_BASE + 0x00) /* 5 bit xxxv vvvv - R/W */
#define SP_STATUS (SPC_REGISTERS_BASE + 0x01) /* 8 bit xxxv vvvv - R/W */
#define SP_CTL2 (SPC_REGISTERS_BASE + 0x02) /* 2 bit xxxx xxvv - R/W */
#define SP_LUT (SPC_REGISTERS_BASE + 0x03) /* 8 bit vvvv vvvv - R/W */
#define SP_XDO (SPC_REGISTERS_BASE + 0x04) /* 10 bit xxxx xxvv vvvv vvvv - R/W */
#define SP_YDO (SPC_REGISTERS_BASE + 0x06) /* 10 bit xxxx xxvv vvvv vvvv - R/W */
#define SP_XD1 (SPC_REGISTERS_BASE + 0x08) /* 10 bit xxxx xxvv vvvv vvvv - R/W */
#define SP_YD1 (SPC_REGISTERS_BASE + 0x0A) /* 10 bit xxxx xxvv vvvv vvvv - R/W */
#define HL_SX (SPC_REGISTERS_BASE + 0x0C) /* 10 bit xxxx xxvv vvvv vvvv - R/W */
#define HL_SY (SPC_REGISTERS_BASE + 0x0E) /* 10 bit xxxx xxvv vvvv vvvv - R/W */
#define HL_EX (SPC_REGISTERS_BASE + 0x10) /* 10 bit xxxx xxvv vvvv vvvv - R/W */
#define HL_EY (SPC_REGISTERS_BASE + 0x12) /* 10 bit xxxx xxvv vvvv vvvv - R/W */
#define SP_SXDO (SPC_REGISTERS_BASE + 0x24) /* 10 bit xxxx xxvv vvvv vvvv - R/W */
#define SP_SYDO (SPC_REGISTERS_BASE + 0x26) /* 10 bit xxxx xxvv vvvv vvvv - R/W */
#define SP_SXD1 (SPC_REGISTERS_BASE + 0x28) /* 10 bit xxxx xxvv vvvv vvvv - R/W */
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