#define SP_SYD1         (SPC_REGISTERS_BASE + 0x2A)      /* 10 bit xxxx xxvv vvvv vvvv - R/W */

#define HL_COLOR        (SPC_REGISTERS_BASE + 0x14)      /* 16 bit vvvv vvvv vvvv vvvv - R/W */
#define HL_CONTR        (SPC_REGISTERS_BASE + 0x16)      /* 16 bit vvvv vvvv vvvv vvvv - R/W */


 /* bit masks for individual STi5500 regs  */

   /*
    * VID_CTL      8 bit reg
    */
#define VIDEO_CTL_EDC           0x01    /* enable decoding */
#define VIDEO_CTL_SRS           0x02    /* software reset */
#define VIDEO_CTL_PRS           0x04    /* pipeline reset */
#define VIDEO_CTL_ERP           0x08    /* auto pipeline reset on pipe error */
#define VIDEO_CTL_SPR           0x20    /* SubPicture Decoder Reset*/
#define VIDEO_CTL_ERS           0x40    /* enable pipeline reset on severe error */
#define VIDEO_CTL_ERU           0x80    /* enable pipeline reset on decode error */

    /*
     * VID_DCF      16 bit reg
     */
#define VIDEO_DCF_BLL         0x2000    /* Blank last line */
#define VIDEO_DCF_BFL         0x1000    /* Blank first line */
#define VIDEO_DCF_FNF         0x0800    /* Frame not field */
#define VIDEO_DCF_FLY         0x0400    /* On the fly */
#define VIDEO_DCF_ORF         0x0200    /* One row per frame */
#define VIDEO_DCF_PXD         0x0040    /* One clock Pixel Delay */
#define VIDEO_DCF_EVD         0x0020    /* Enable Video Display */
#define VIDEO_DCF_EOS         0x0010    /* Enable OSD */
#define VIDEO_DCF_DSR         0x0008    /* Disable Sample Rate Convertor*/
#define VIDEO_DCF_VFC         0x0007    /* Vert. Filter Configuration*/
#define VIDEO_DCF_VFC2        0x0004
#define VIDEO_DCF_VFC1        0x0002
#define VIDEO_DCF_VFC0        0x0001
#define VIDEO_DCF_VFC_MASK    0x0007    /* (3) VCF values */

    /*
    * VID_HDS      3 bit reg
     */
#define VIDEO_HDS_START         0x01    /* start header search */
#define VIDEO_HDS_QMI           0x02    /* select intra Q table for loading */
#define VIDEO_HDS_QMN           0x00    /* select non-intra Q table for loading */
#define VIDEO_HDS_SOS           0x04    /* must be set LOW */

    /*
     * VID_ITM/ VID_ITS/ VID_STA    24 bit reg
     *      [24:16] is read/ write from different address. so we are
     *      going to deal us two reg eg., VID_ITM_HIGH & VID_ITM
     */
#define VIDEO_INT_HIGH_NDP      0x80    /* new discarded packet */
#define VIDEO_INT_HIGH_ERR      0x40    /* Inconsistancy err in PES parser */
#define VIDEO_INT_HIGH_SCR      0x20    /* new SCR latched */
#define VIDEO_INT_HIGH_HAF      0x10    /* History FIFO almost full */
#define VIDEO_INT_HIGH_ABF      0x08    /* Audio BitBuff FULL */
#define VIDEO_INT_HIGH_RFN      0x04    /* Read FIFO notEMPTY */
#define VIDEO_INT_HIGH_WFN      0x02    /* Write FIFO notFULL */
#define VIDEO_INT_HIGH_ABE      0x01    /* Audio BitBuff EMPTY */

#define VIDEO_INT_PDE   0x8000          /* Pict decoding or Underflow error */
#define VIDEO_INT_SER   0x4000          /* Severe or Overflow error */
#define VIDEO_INT_BMI   0x2000          /* Block Move Idle */
#define VIDEO_INT_HFF   0x1000          /* Header FIFO full */
#define VIDEO_INT_PNC   0x0800          /* Header FIFO empty */
#define VIDEO_INT_ERC   0x0400          /* Error Concealement */
#define VIDEO_INT_PID   0x0200          /* Pipeline Idle */
#define VIDEO_INT_PSD   0x0080          /* Dsync - Decode start */
#define VIDEO_INT_VST   0x0040          /* Top(Odd) Vsync */
#define VIDEO_INT_VSB   0x0020          /* Bottom(Even) Vsync */
#define VIDEO_INT_BBE   0x0010          /* Video Bitbuff empty */
#define VIDEO_INT_BBF   0x0008          /* Video Bitbuff full */
#define VIDEO_INT_HFE   0x0004          /* Header FIFO empty */
#define VIDEO_INT_CFF   0x0002          /* CD Fifo full */
#define VIDEO_INT_SCH   0x0001          /* Start Code Hit */

    /*
     * VID_PFH      8 bit reg
     */
#define VIDEO_PFH_BFH           0xF0    /* (4) backward_horz_f_code */
#define VIDEO_PFH_FFH           0x0F    /* (4) forward_horz_f_code */

#define VIDEO_PFH_BFH_SHIFT     0x04    /* backward_horz_f_code position */

    /*
     * VID_PFV      8 bit reg
     */
#define VIDEO_PFV_BFV           0xF0    /* (4) backward_vert_f_code */
#define VIDEO_PFV_FFV           0x0F    /* (4) forward_vert_f_code */

#define VIDEO_PFV_BFV_SHIFT     0x04    /* backward_vert_f_code position */

    /*
     * VID_PPR1     6 bit reg
     */
#define VIDEO_PPR1_PCT          0x30    /* (2) pict_coding_type */
#define VIDEO_PPR1_DCP          0x0C    /* (2) intra_dc_precision */
#define VIDEO_PPR1_PST          0x03    /* (2) pict_struct */
#define VIDEO_PPR1_OTF          0x40    /* B On the Fly bit */

    /*
     * VID_PPR2     6 bit reg
     */
#define VIDEO_PPR2_TFF          0x20    /* Top Field First */
#define VIDEO_PPR2_FRM          0x10    /* frame_pred_frame_dct */
#define VIDEO_PPR2_CMV          0x08    /* concealment_motion_vectors */
#define VIDEO_PPR2_QST          0x04    /* q_scale_type */
#define VIDEO_PPR2_IVF          0x02    /* intra_vlc_format */
#define VIDEO_PPR2_AZZ          0x01    /* alternate_scan */

    /*
     * VID_TIS      7 bit reg
     */
#define VIDEO_TIS_MP2           0x40    /* mpeg2 mode */
#define VIDEO_TIS_SKIP          0x30    /* (2) skip modempeg2 mode */
#define VIDEO_TIS_OVW           0x08    /* Overwrite Mode */
#define VIDEO_TIS_FIS           0x04    /* Force Instruction */
#define VIDEO_TIS_RPT           0x02    /* Reapeat Mode */
#define VIDEO_TIS_EXE           0x01    /* Execute the next Task */
#define VIDEO_TIS_SKIP_MASK     0x30    /* skip bit flags position */

#define NO_SKIP                 0x00    /* Dont skip any picture */
#define SKIP_ONE_DECODE_NEXT    0x10    /* skip one pict and decode next pict */
#define SKIP_TWO_DECODE_NEXT    0x20    /* skip two pict and decode next pict */
#define SKIP_ONE_STOP_DECODE    0x30    /* skip one pict and stop decoder */

    /*
     * VID_TRF     12 bits reg
     */
#define VIDEO_TRF_DTR         0x0400    /* Disable temporal reference */
#define VIDEO_TRF_DC2         0x0800    /* Redecode same B-frame twice */
#define VIDEO_TRF_TRF         0x03FF    /* Mask on Temporal Reference 10-bits */

    /*
     * VID_LDP     1 bit reg
     */
#define VIDEO_LDP_SET           0x01    /* Load start code detector pointer */
#define VIDEO_LDP_RESET         0x00    /* */

    /* VID_SM      12 bit reg */
#define VIDEO_SM_INT_SHIFT     0x04    /* shift to get integer part in low bits */
#define VIDEO_SM_INT_MASK     0xFFF    /* maximum integer part */
#define VIDEO_SM_FRACT_MASK    0x0F    /* mask to get fraction part */

    /* VID_SCN      9 bit reg */
#define VIDEO_SCN_MASK         0x1FF    /* mask to max size */

    /*
     * PES_CF1      8 bit reg
     */
#define PES_CF1_SDT             0x80    /* store DTS not PTS */
#define PES_CF1_IAI             0x20    /* Ignore Audio Stream ID */
#define PES_CF1_AUD_STREAM_ID   0x1F    /* (5) Audio Stream Id */

    /*
     * PES_CF2      8 bit reg
     */
#define PES_CF2_MODE            0xC0    /* (2) mode of Video Stream Parser */
#define PES_CF2_SS              0x20    /* System or elementary stream */
#define PES_CF2_IVI             0x10    /* Ignore Video Stream ID */
#define PES_CF2_VID_STREAM_ID   0xF     /* (4) Video Stream Id */

    /*
     * PES_TM2      2 bit READ ONLY reg
     */
#define PES_TM2_M2              0x02    /* MPEG2 not MPEG1  in automatic mode */
#define PES_TM2_DSA             0x01    /* DSM association flag */



    /*
     * CFG_CCF      8 bit reg
     */
#define CFG_CCF_EAI             0x80    /* Enable Audio Interface */
#define CFG_CCF_EOU             0x40    /* Enable Ovf/Udf errors  */
#define CFG_CCF_PBO             0x20    /* Prevent Bitbuffer Overflow */
#define CFG_CCF_EC3             0x10    /* Enable Clock 3 */
#define CFG_CCF_EC2             0x08    /* Enable Clock 2 */
#define CFG_CCF_ECK             0x04    /* Enable Clocks */
#define CFG_CCF_EDI             0x02    /* Enable Display Interface */
#define CFG_CCF_EVI             0x01    /* Enable Video Interface */

    /*
     * CFG_DRC      7 bit reg
     */
#define CFG_DRC_MRS             0x20    /* Mode register set            */
#define CFG_DRC_P1              0x08    /* Clk3 to mem Clk phase bit 1  */
#define CFG_DRC_P0              0x04    /* Clk3 to mem Clk phase bit 0  */
#define CFG_DRC_ERQ             0x02    /* Enable task_t requests      */
#define CFG_DRC_SDR             0x01    /* sync DRAM mode               */

    /*
     * CFG_GCF      7 bit reg
     */
#define CFG_GCF_A3DI            0x40    /* AC3 ext data strobe mode */
#define CFG_GCF_A3RQ            0x20    /* AC3 ext data strobe mode */
#define CFG_GCF_SP_INPUT        0x10    /* SP data input to CDR */
#define CFG_GCF_VID_INPUT       0x18    /* Video data input to CDR */
#define CFG_GCF_AUD_INPUT       0x08    /* Audio data input to CDR */
#define CFG_GCF_EXT_INPUT       0x00    /* Ext strobes selected */
#define CFG_GCF_SCK             0x04    /* Audio Strobe Clock select */
#define CFG_GCF_A3M             0x02    /* Select AC3 decoder/Not Mpeg*/
#define CFG_GCF_ACS             0x01    /* has to be reset !!!*/

    /*
     * CFG_MCF      8 bit reg
     */
#define CFG_MCF_M20             0x80    /* select 20 Mbit mode */
#define CFG_MCF_RFI             0x7F    /* (7) DRAM refresh interval */

    /*
     * CKG_AUD/ CKG_AUX, CKG_MCK, CKG_PIX, CKG_PCM, CKG_VID
     */
#define CKG_XXX_DIV             0x40    /* enable frac divider */
#define CKG_XXX_ENABLE_FRAC_DIV 0x20    /* enable frac divider */
#define CKG_XXX_DIV2            0x10    /* divide by 2 the o/p of frac divider */

    /*
     * CKG_CFG  8 bit reg
     */
#define CKG_CFG_AUX_ENABLE      0x80    /* enable AUX clock */
#define CKG_CFG_MEM_CLK_IN      0x40    /* MEM_CLK is an i/p */
#define CKG_CFG_MEM_CLK_OUT     0x00    /* MEM_CLK is an o/p */
#define CKG_CFG_PCM_CLK_IN      0x00    /* PCM_CLK is an i/p */
#define CKG_CFG_PCM_CLK_OUT     0x20    /* PCM_CLK is an o/p */
#define CKG_CFG_PIX_CLK_IN      0x00    /* PIX_CLK is an i/p */
#define CKG_CFG_PIX_CLK_OUT     0x10    /* PIX_CLK is an o/p */
#define CKG_CFG_AUX_MUX_AUX     0x00    /* output CKG_AUX */
#define CKG_CFG_AUX_MUX_VID     0x04    /* output VIDEO_AUX **TEST MODE** */
#define CKG_CFG_AUX_MUX_LNK     0x08    /* LNK_CLK is an i/p on aux_clk_out */
#define CKG_CFG_AUX_MUX_PLL     0x0C    /* output f_PLL **TEST MODE** */
#define CKG_CFG_LNK_CLK_IN      0x00    /* LNK_CLK is an i/p on a_pts_stb */
#define CKG_CFG_LNK_CLK_OUT     0x02    /* LNK_CLK is an o/p */

    /*
     * VID_FRZ     1 bit reg
     */
#define VIDEO_FRZ               0x01    /* Freeze the display */
#define NO_FREEZE               0x00

    /*
     * VID_PPR2     6 bit reg
     */
#define VIDEO_PPR2_TFF          0x20    /* Top Field First */
#define VIDEO_PPR2_FRM          0x10    /* frame_pred_frame_dct */
#define VIDEO_PPR2_CMV          0x08    /* concealment_motion_vectors */
#define VIDEO_PPR2_QST          0x04    /* q_scale_type */
#define VIDEO_PPR2_IVF          0x02    /* intra_vlc_format */
#define VIDEO_PPR2_AZZ          0x01    /* alternate_scan */


#ifdef STI5500_VERSION_A
    /*
     * DENC_R01 8 bit reg
     */
#define DENC_R01_DACINV         0x80    /* DAC input data inversion */

#else
  /* ---- CFG0 */
  #define DENC_CFG0_STD1     0x80  /*  Standard selection */
  #define DENC_CFG0_STD0     0x40  /*  Standard selection */
  #define DENC_CFG0_SYNC2    0x20  /*  Synchro source */
  #define DENC_CFG0_SYNC1    0x10  /*  Free Run */
  #define DENC_CFG0_SYNC0    0x08  /*  Frame synchronisation source in slave mode */
  #define DENC_CFG0_POLH     0x04  /*  Synchro : VCS polarity */
  #define DENC_CFG0_POLV     0x02  /*  Frame synchro : ODD/EVEN polarity */
  #define DENC_CFG0_MOD      0x01  /*  Slave/Master */

  /* ---- CFG1 */
  #define DENC_CFG1_BLKLI    0x80  /*  Blanking lines */
  #define DENC_CFG1_FLT1     0x40  /*  Chroma pass band filter */
  #define DENC_CFG1_FLT0     0x20  /*  Chroma pass band filter extension */
  #define DENC_CFG1_SYNCOK   0x10  /*  Synchro availability in case of no free-run active */
  #define DENC_CFG1_COKI     0x08  /*  Color kill */
  #define DENC_CFG1_SETUP    0x04  /*  Blanking level */
  #define DENC_CFG1_CC2      0x02  /*  Close caption */
  #define DENC_CFG1_CC1      0x01  /*  Close caption */

  /* ---- CFG2 */
  #define DENC_CFG2_NINTRL   0x80  /*  Non Interlaced Mode */
  #define DENC_CFG2_ENRST    0x40  /*  Cyclic update of DDFS */
  #define DENC_CFG2_BURSTEN  0x20  /*  Chrominance Burst control */
  #define DENC_CFG2_SELRST   0x08  /*  select reset */
  #define DENC_CFG2_RSTOSC   0x04  /*  SOftware Reset of DDFS */
  #define DENC_CFG2_VALRST1  0x02  /*  Phase oscillator reset */
  #define DENC_CFG2_VALRST0  0x01  /*  Phase oscillator reset */

  /* ---- CFG3 */
  #define DENC_CFG3_ENTRAP   0x80  /*  Enable trap filter */
  #define DENC_CFG3_TRAPPAL  0x40  /*  Select NTSC trap filter or PAL trap filter */
  #define DENC_CFG3_ENCGMS   0x20  /*  Encoding enable */
  #define DENC_CFG3_NOSD     0x10  /*  Choice of active edge of CKREF */
  #define DENC_CFG3_DEL2     0x08  /*  Delay on luma path */
  #define DENC_CFG3_DEL1     0x04  /*  */
  #define DENC_CFG3_DEL0     0x02  /*  */

  /* ---- CFG4 */
  #define DENC_CFG4_SYNCINAD1  0x80  /*  adjustement of incoming sync signal */
  #define DENC_CFG4_SYNCINAD0  0x40  /*  " */
  #define DENC_CFG4_SYNCOUTAD1 0x20  /*  adjustement of outgoing sync signal */
  #define DENC_CFG4_SYNCOUTAD0 0x10  /*  " */
  #define DENC_CFG4_ALINE      0x08  /*  Pure digital / Anlog-like composite video signal */
  #define DENC_CFG4_TXDL2      0x04  /*  Teletext data latency */
  #define DENC_CFG4_TXDL1      0x02  /*  " */
  #define DENC_CFG4_TXDL0      0x01  /*  " */

  /* ---- CFG5 */
  #define DENC_CFG5_BKCVBS  0x40  /*  blanking of DAC CVBS */
  #define DENC_CFG5_BKYS    0x20  /*  blanking of DAC G/Y */
  #define DENC_CFG5_BKC     0x10  /*  blanking of DAC R/C */