?? gpif.c
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// This program configures the General Programmable Interface (GPIF) for FX2.
// Parts of this program are automatically generated using the GPIF Tool V2.40 [700].
// Please do not modify sections of text which are marked as "DO NOT EDIT ...".
// You can modify the comments section of this GPIF program file using the dropdown menus
// and pop-up dialogs. These controls are available as hot spots in the text. Modifying the
// comments section will generate program code which will implement your GPIF program.
//
// DO NOT EDIT ...
// GPIF Initialization
// Interface Timing Async
// Internal Ready Init IntRdy=1
// CTL Out Tristate-able Binary
// SingleWrite WF Select 3
// SingleRead WF Select 2
// FifoWrite WF Select 1
// FifoRead WF Select 0
// Data Bus Idle Drive Tristate
// END DO NOT EDIT
// DO NOT EDIT ...
// GPIF Wave Names
// Wave 0 = FIFORd
// Wave 1 = FIFOWr
// Wave 2 = SnglRd
// Wave 3 = SnglWr
// GPIF Ctrl Outputs Level
// CTL 0 = CTL 0 CMOS
// CTL 1 = CTL 1 CMOS
// CTL 2 = CTL 2 CMOS
// CTL 3 = CS CMOS
// CTL 4 = RD CMOS
// CTL 5 = WR CMOS
// GPIF Rdy Inputs
// RDY0 = RDY0
// RDY1 = RDY1
// RDY2 = RDY2
// RDY3 = RDY3
// RDY4 = RDY4
// RDY5 = RDY5
// FIFOFlag = FIFOFlag
// IntReady = IntReady
// END DO NOT EDIT
// DO NOT EDIT ...
//
// GPIF Waveform 0: FIFORd
//
// Interval 0 1 2 3 4 5 6 Idle (7)
// _________ _________ _________ _________ _________ _________ _________ _________
//
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data
// NextData SameData SameData SameData SameData SameData SameData SameData
// Int Trig No Int No Int No Int No Int No Int No Int No Int
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
// Term A
// LFunc
// Term B
// Branch1
// Branch0
// Re-Exec
// Sngl/CRC Default Default Default Default Default Default Default
// CTL 0 1 1 1 1 1 1 1 1
// CTL 1 1 1 1 1 1 1 1 1
// CTL 2 1 1 1 1 1 1 1 1
// CS 1 1 1 1 1 1 1 1
// RD 1 1 1 1 1 1 1 1
// WR 1 1 1 1 1 1 1 1
//
// END DO NOT EDIT
// DO NOT EDIT ...
//
// GPIF Waveform 1: FIFOWr
//
// Interval 0 1 2 3 4 5 6 Idle (7)
// _________ _________ _________ _________ _________ _________ _________ _________
//
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data
// NextData SameData SameData SameData SameData SameData SameData SameData
// Int Trig No Int No Int No Int No Int No Int No Int No Int
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
// Term A
// LFunc
// Term B
// Branch1
// Branch0
// Re-Exec
// Sngl/CRC Default Default Default Default Default Default Default
// CTL 0 1 1 1 1 1 1 1 1
// CTL 1 1 1 1 1 1 1 1 1
// CTL 2 1 1 1 1 1 1 1 1
// CS 1 1 1 1 1 1 1 1
// RD 1 1 1 1 1 1 1 1
// WR 1 1 1 1 1 1 1 1
//
// END DO NOT EDIT
// DO NOT EDIT ...
//
// GPIF Waveform 2: SnglRd
//
// Interval 0 1 2 3 4 5 6 Idle (7)
// _________ _________ _________ _________ _________ _________ _________ _________
//
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
// DataMode NO Data NO Data NO Data Activate NO Data NO Data NO Data
// NextData SameData SameData SameData SameData SameData SameData SameData
// Int Trig No Int No Int No Int No Int No Int No Int No Int
// IF/Wait Wait 5 Wait 1 Wait 5 Wait 2 Wait 1 Wait 1 Wait 1
// Term A
// LFunc
// Term B
// Branch1
// Branch0
// Re-Exec
// Sngl/CRC Default Default Default Default Default Default Default
// CTL 0 1 1 1 1 1 1 1 1
// CTL 1 1 1 1 1 1 1 1 1
// CTL 2 1 1 1 1 1 1 1 1
// CS 1 0 0 0 1 1 1 1
// RD 1 1 0 1 1 1 1 1
// WR 1 1 1 1 1 1 1 1
//
// END DO NOT EDIT
// DO NOT EDIT ...
//
// GPIF Waveform 3: SnglWr
//
// Interval 0 1 2 3 4 5 6 Idle (7)
// _________ _________ _________ _________ _________ _________ _________ _________
//
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
// DataMode NO Data NO Data Activate Activate NO Data NO Data NO Data
// NextData SameData SameData SameData SameData SameData SameData SameData
// Int Trig No Int No Int No Int No Int No Int No Int No Int
// IF/Wait Wait 5 Wait 1 Wait 5 Wait 1 Wait 1 Wait 1 Wait 1
// Term A
// LFunc
// Term B
// Branch1
// Branch0
// Re-Exec
// Sngl/CRC Default Default Default Default Default Default Default
// CTL 0 1 1 1 1 1 1 1 1
// CTL 1 1 1 1 1 1 1 1 1
// CTL 2 1 1 1 1 1 1 1 1
// CS 1 0 0 0 1 1 1 1
// RD 1 1 1 1 1 1 1 1
// WR 1 1 0 1 1 1 1 1
//
// END DO NOT EDIT
// GPIF Program Code
// DO NOT EDIT ...
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h" // SYNCDELAY macro
// END DO NOT EDIT
// DO NOT EDIT ...
const char xdata WaveData[128] =
{
// Wave 0
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* Output*/ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
/* LFun */ 0x00, 0x09, 0x12, 0x12, 0x00, 0x2D, 0x12, 0x3F,
// Wave 1
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* Output*/ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
/* LFun */ 0x09, 0x09, 0x12, 0x12, 0x00, 0x2D, 0x36, 0x3F,
// Wave 2
/* LenBr */ 0x05, 0x01, 0x05, 0x02, 0x01, 0x01, 0x01, 0x07,
/* Opcode*/ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
/* Output*/ 0xFF, 0xF7, 0xE7, 0xF7, 0xFF, 0xFF, 0xFF, 0xFF,
/* LFun */ 0x00, 0x09, 0x12, 0x3F, 0x00, 0x2D, 0x12, 0x3F,
// Wave 3
/* LenBr */ 0x05, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x07,
/* Opcode*/ 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00,
/* Output*/ 0xFF, 0xF7, 0xD7, 0xF7, 0xFF, 0xFF, 0xFF, 0xFF,
/* LFun */ 0x09, 0x09, 0x12, 0x3F, 0x00, 0x2D, 0x36, 0x3F
};
// END DO NOT EDIT
// DO NOT EDIT ...
const char xdata InitData[7] =
{
/* Regs */ 0x80,0x00,0x00,0xFF,0x06,0xE4,0x11
};
// END DO NOT EDIT
// TO DO: You may add additional code below.
void GpifInit( void )
{
BYTE i;
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
// 8051 doesn't have access to waveform memories 'til
// the part is in GPIF mode.
IFCONFIG = 0xCE;
// IFCLKSRC=1 , FIFOs executes on internal clk source
// xMHz=1 , 48MHz internal clk rate
// IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
// ASYNC=1 , master samples asynchronous
// GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
// IFCFG[1:0]=10, FX2 in GPIF master mode
GPIFABORT = 0xFF; // abort any waveforms pending
GPIFREADYCFG = InitData[ 0 ];
GPIFCTLCFG = InitData[ 1 ];
GPIFIDLECS = InitData[ 2 ];
GPIFIDLECTL = InitData[ 3 ];
GPIFWFSELECT = InitData[ 5 ];
GPIFREADYSTAT = InitData[ 6 ];
// use dual autopointer feature...
AUTOPTRSETUP = 0x07; // inc both pointers,
// ...warning: this introduces pdata hole(s)
// ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
// source
APTR1H = MSB( &WaveData );
APTR1L = LSB( &WaveData );
// destination
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