0      0      1      Screen data (Transparent cursor)
            1      0      1      Palette index 0 ?
            0      1      1      Screen data (Transparent cursor)
            1      1      1      Palette index 255 ?

3d4h index 46h (R/W):                                                   (9440)
bit 0-5  Cursor Horizontal hotspot. The position (in pixels from the left) of
         the cursor hotspot within the 32x32 or 64x64 map. The displayed cursor
         starts at the hotspot and ends 32/64 pixels from the left edge (i.e.
         it does not wrap to the next line).

3d4h index 47h (R/W):                                                   (9440)
bit 0-5

3d4h index 50h (R/W):                                                   (9440)
bit    0  Set for 64x64 cursor, clear for 32x32 cursor
       6  Clear for Cursor Style 0 (Windows?), set for Cursor Style 1 (X11?)
       7  Enable hardware cursor if set

3D8h (R/W):  Destination Segment Register                    (8900CL/D,9200 +)
bit 0-4  Bank number in 64k units. If 3CEh index Fh bit 0 is set this is the
         write bank, if not the combined read/write bank.
         This register is only active if 3CEh index Fh bit 2 is set.

3D9h (R/W):  Source Segment Register                         (8900CL/D,9200 +)
bit 0-4  If 3CEh index Fh bit 0 is set this is the read bank.
         This register is only active if 3CEh index Fh bit 2 is set.


Note: Ferraro (in Programmer's Guide to... 3rd edition) documents the
      accelerator registers at 21xAh for the later Tridents, however so far
      I have been unable to verify this.


43C6h W(R/W):  Memory Clock                                             (9440)
bit 0-15  Selects the memory clock. 2C6h = 50MHz, 307h = 58MHz, 87h = 64MHz
            8Eh = 75MHz
Note: 3C4h index Eh (new) bits 1 & 7 must be set to update this register

43C8h W(R/W):  Video Clock                                              (9440)
bit 0-15  Selects the video clock when 3C2/Ch bits 2-3 = 2.
Note: 3C4h index Eh (new) bits 1 & 7 must be set to update this register


46E8h (R):  Video Subsystem Enable Register
bit 3  Enable VGA if set


The memory mapped registers appears to be mapped at BFF00h (how to enable
them ?). Probably only exists on the 9440 and later (9420?)

M+20h (R?)
bit   5  Set when the graphics engine is busy?
      6  Set if ?  Data transfers should wait for it to clear?
      7  Set when ?

M+22h (R/W):
bit  0-?  9 for non-8bit modes, 4 for 8bit modes (<=1024), 8 for other modes

M+24h (R/W):
bit  0-2  Write 1 to start a Blit, 4 to start a line draw ?

M+27h (R/W):
bit  0-7  Raster op (=Bits 16-23 of the Windows ROP3).

M+28h W(R/W):
bit    2  Set when using pattern ??
       5  Set when using pattern ??
       6  ??
       8  If set the Blit moves bottom-to-top (decreasing address), if clear
          it is top-to-bottom (increasing address).
       9  If set the Blit moves right-to-left (decreasing address), if clear
          it is left-to-right (increasing address).
      14  Set for solid fills ??

M+2Bh (R/W):
bit  0-2  Offset into the pattern ?

M+2Ch W(R/W):
bit 0-  Background color

M+30h W(R/W):
bit 0-  Foreground color

M+34h W(R/W):
bit 0-15  Address of ?pattern? in units of 64bytes

M+38h W(R/W):
bit 0-  Destination starting X-coordinate

M+3Ah W(R/W):
bit 0-  Destination starting Y-coordinate

M+3Ch W(R/W):
bit 0-  Source starting X-coordinate

M+3Eh W(R/W):
bit 0-  Source starting Y-coordinate

M+40h W(R/W):
bit 0-  Width of the Blit area in pixels

M+42h W(R/W):
bit 0-  Height of the Blit area in scanlines

M+44h

M+46h W(R/W):

  Bank selection:

    Trident VGAs (except 8800BR) can operate in 2 different modes:

    Old Mode, with a 128k window to display memory at A000h - BFFFh
    and New Mode, with a 64k window to display memory at A000h - AFFFh.
    Old/New mode is selected by reading/writing the Chip Version Register
    (3C4h index 0Bh).
    Each mode has its own registers at 3C4h index 0Dh and 0Eh.


  ID Trident VGA:

    wrinx($3C4,$B,0);    {Force old_mode_registers}
    chp:=inp($3C5);      {Read chip ID and switch to new_mode_registers}
    old:=rdinx($3C4,$E);
    outp($3C5,0);
    value:=inp($3C5) and $F;
    outp($3C5,old);

    if value=2 then
    begin
      outp($3C5,old xor 2);
      case chp of
        1:Trident TR8800BR;
        2:Trident TR8800CS;
        3:Trident TR8900;
    4,$13:Trident TR8900C;
      $23:Trident TR9000;
      $33:Trident TR8900CL or D;
      $43:Trident TR9000i;
      $53:Trident TR8900CXr
      $63:Trident LCD9100B;
      $83:Trident LX8200;
      $93:Trident TVGA9400CXi
      $A3:Trident LCD9320;
  $73,$F3:Trident GUI9420;
      end;
    end
    else if (chp=1) and testinx2($3C4,$E,6) then
           Trident TVGA 8800BR     {Haven't tested this yet}

  Video Modes:
    50h  T    80   30  16  (8x16)
    51h  T    80   43  16  (8x11)
    52h  T    80   60  16  (8x8)
    53h  T   132   25  16  (8x14)
    54h  T   132   30  16  (8x16)
    55h  T   132   43  16  (8x11)
    56h  T   132   60  16  (8x8)
    57h  T   132   25  16  (9x14)
    58h  T   132   30  16  (9x16)
    59h  T   132   43  16  (9x11)
    5Ah  T   132   60  16  (9x8)
    5Bh  G   800  600  16  PL4
    5Ch  G   640  400 256  P8
    5Dh  G   640  480 256  P8
    5Eh  G   800  600 256  P8      (Undocumented on 8800)
    5Fh  G  1024  768  16  PL4
    60h  G  1024  768   4          8900 Only
    61h  G   768 1024  16  PL4
    62h  G  1024  768 256  P8      8900 Only
    63h  G  1280 1024  16  PL4     Which chip/BIOS rev ?
    64h  G  1280 1024 256  P8      8900CL only
    6Ah  G   800  600  16  PL4     Newer boards
    6Bh  G   320  200 16m  P24     TVGA9000i+
    6Ch  G   640  480 16m  P24     8900CL+
    6Dh  G   800  600 16m  P24     8900CL+

    70h  G   512  480 32K  P15     89xx with Sierra DAC
    71h  G   512  480 64K  P16     89xx with Sierra DAC
    74h  G   640  480 32K  P15     89xx with Sierra DAC
    75h  G   640  480 64K  P16     89xx with Sierra DAC
    76h  G   800  600 32K  P15     89xx with Sierra DAC
    77h  G   800  600 64K  P16     89xx with Sierra DAC
    78h  G  1024  768 32K  P15     8900CL with Sierra DAC
    79h  G  1024  768 64K  P16     8900CL with Sierra DAC
    7Eh  G   320  200 32K  P15     TVGA9000i
    7Fh  G   320  200 64K  P16     TVGA9000i

    ZyMOS POACH51 modes:

    60h  G   960  720  16  PL4
    61h  G  1280  640  16  PL4
    62h  G   512  512 256  P8
    63h  G   720  540  16  PL4
    64h  G   720  540 256  P8
    6Ah  G   800  600  16  PL4


  Everex Viewpoint use Everex modes.


Note: The TVGA9000i has an on-chip DAC with 32k/64k capability.
      The BIOS on the card I have (BIOS version D3.51) doesn't
      seem to handle the Hi/True color modes correctly.
      I have managed to get the 320x200 32k/64k modes working by programming
      the DAC command register directly, but the 512x480 modes and the 320x200
      16m mode still doesn't work



  Bios extensions:

----------1000-------------------------------
INT 10 - VIDEO - SET VIDEO MODE
        AH = 00h
        AL = mode number
Return: AH = Status of call:  (Trident Super VGA Chips)

                    Trident 8800                Trident 8900
             00h   Successful                      do
             80h   Fail. Wrong switch              do
             81h   Insufficient Video              do
                   Memory.
             82h   The 36MHz crystal            Mode not supported
                   cannot support the mode
             83h   The 40MHz crystal            Mode not supported
                   cannot support the mode.
             84h   The 44.9MHz crystal          Mode not supported
                   cannot support the mode.
             85h   Dead or no crystal
             86h                               Wrong CRTC base for dual screen
             87h                               Text mode not supported
Note: The return code appears to be unsupported on some newer Trident
      card, i.e. 9440AGi
----------1012-BL11------------------------------
INT 10 - VIDEO - Trident BIOS - Get BIOS Info
        AH = 12h
        BL = 11h
Return: AL = 12h if function supported
        ES:BP -> BIOS info structure:
                 Offset:  Size:   Description:
                   00h    BYTE    ??? (=0)
                   01h    BYTE    OEM Code (00h for original Trident)
                   02h    WORD    ID ?? (1073h for 8800BR, 1074h for 8800CS,
                                   1090h for 8900C or 9000i
                   04h  8 BYTEs   BIOS date ('mm/dd/yy')
                   0Ch    WORD    ???
                   0Eh  8 BYTEs   BIOS Version (' C3-128 ', ' C3-129 ',
                                    ' D3.51  ').
----------1012-BL12------------------------------
INT 10 - VIDEO - Trident BIOS - GET VIDEO RAM SIZE
        AH = 12h
        BL = 12h
Return: AL = 12h if function supported
        AH = number of 256K banks of RAM installed
----------101200-BL14----------------------------
INT 10 - VIDEO - Trident LOCKFIFO - Get FIFO state
        AX = 1200h
        BH = 14h
Return: CX = FIFO state
Note: Implemented by the LOCKFIFO.COM utility
----------101201-BL14----------------------------
INT 10 - VIDEO - Trident LOCKFIFO - Get FIFO state
        AX = 1201h
        BH = 14h
        CX = FIFO state (0..FFh, FFh = disabled)
Note: Implemented by the LOCKFIFO.COM utility