IBM XGA      1024*768 interlaced
  IBM XGA-NI   1024*768 Non-interlaced

All register accesses happen through a block of 16 registers starting
at a adapter dependent register (called xga in the following).
The register xga+0Ah works as an indexed register i.e.. xga+0Ah is the
index register and xga+0Bh is the data register.

Also a block of 128 bytes memory mapped registers exists, primarily used for
the accelerator functions.

General note:
When writing to XGA registers undefined bits must be set to 0 unless
otherwise specified. When reading the undefined bits may be truly undefined,
i.e. random.

0100h  W(R):  Identification Word
bit  0-15  Identification Word ID'ng the XGA board.
             8FDAh = The IBM XGA-NI.
             8FDBh = Original IBM XGA
             (8FD8h-8FDBh is reserved for IBM XGA's).
           VESA defines the following ranges for XGA compatible boards:
             240h-27Fh, 830h-0A7F, 0A90h-0BFFh and 8FD0h-8FD3h(reserved)
Note: POS register access must be enabled.

0102h  (R/W):  XGA Configuration Register
bit     0  XGA_ENABLE. If set the XGA registers can be accessed, when cleared
           only the POS registers (100h-105h) can be accessed.
      1-3  INSTANCE. IDs the particular XGA adapter (there can be up to 8 in
           a system). This value is used to define the XGA base address
           (21x0h) and which 128 byte block of the 1KB external memory the
           memory mapped registers are located in.
      4-7  EXT_MEM_ADDR. Defines the address the 8KB (usually 7KB ROM and 1KB
           dedicated to XGA memory mapped registers) external memory is mapped
           to:
             0 = 0C000h,  1 = 0C2000h,  2 = 0C4000h,  3 = 0C6000h
             4 = 0C800h,  5 = 0CA000h,  6 = 0CC000h,  7 = 0CE000h
             8 = 0D000h,  9 = 0D2000h, 0A = 0D4000h, 0B = 0D6000h
            0C = 0D800h, 0D = 0DA000h, 0E = 0DC000h, 0F = 0DE000h
           The external memory can be disabled by clearing the EXT_MEM_ENABLE
           bit in the Bus Arbitration Register (103h).

0103h  (R/W):  Bus Arbitration Register
bit     1  EXT_MEM_ENABLE. If set the 8KB external memory block can be
           accesses, if clear only the 1KB memory mapped registers can be
           accessed.
        2  FAIR_ENABLE. If set the MCA fairness protocol is enabled.
      3-6  ARB_LEVEL. The MCA bus arbitration level.
Note: for VESA systems set 106h to 0 to access this register.

0104h  (R/W):  Display Memory Base Address
bit     0  DISP_MEM_ACCESS. If set the display memory is mapped as a
           contiguous 4MB chunk at the address described below.
      1-7  DISP_MEM_BASE. The upper 7 bits (25-31) of the display memory
           address. Bit 22-24 is taken from the INSTANCE field of register
           102h.
Note: for VESA local bus systems set 106h to 0 to access this register.

0104h index 1 (R):  Manufactor ID low                                   (VESA)
bit   0-7  Low byte of manufactor ID.
Note: Set 106h to 1 to read this register
Note: This register may be implemented as Read only or Read/Write.

0104h index 2 (R):  Manufactor ID high                                  (VESA)
bit   0-7  High byte of manufactor ID.
           This register is optional and reads as 0 if not implemented
Note: Set 106h to 2 to read this register
Note: This register may be implemented as Read only or Read/Write.

0104h index 3 (R/W):  VGA BIOS Configuration                            (VESA)
bit     0  VGA BIOS ROM Decode Enabled if set
      1-3  VGA BIOS ROM Decode Location. VGA BIOS ROM at:
             0: C000h, 1: C800h, 2: D000h, 3: D800h, 4: E000h, 5: E800h
Note: Set 106h to 1 to read this register

0105h  (R/W):  1MB Aperture Base Address
bit   0-3  BASE_1MB. Determines the address of the 1MB aperture where the
           video memory will be mapped. 0 indicates that a 1MB block could not
           be found in the lower 16MB of the address space.
Note: When writing to this register bits 4-7 must be written as 1101b,
      i.e.. 0BFh.

0106h  W(W):  POS index                                                 (VESA)
bit  0-15  This register determines the content of register 0103h and 0104h.
           Values 4-0Fh are reserved. When this register is 0 the registers at
           0103h and 0104h are fully compatible with the IBM XGA and XGA-NI.
           For 0103h only index 0 is defined, for 0104 index 0-3 are defined.

0109h (R/W):  ISA POS Enable                                      (VESA - ISA)
bit   0-2  Instance Number (must match the instance (i.e.. 1) to enable)
        3  Setup Mode Enable. If set the POS registers (0100h-0107h) may be
           accessed.
Note: VESA reserves 0108h-010Fh for systems with more than one XGA, but
      currently only implements instance 1 (0109h).

21x0h  (R/W):  Operating Mode Register
bit   0-2  DISPLAY_MODE.
             0 = VGA mode, disable XGA address decode
             1 = VGA mode, enable XGA address decode
             2 = 132 column text mode, disable XGA address decode
             3 = 132 column text mode, enable XGA address decode.
             4 = XGA Extended Graphics mode.
        3  REG_FORMAT. If set the memory mapped registers use Motorola or
           "Big-endian" format rather than Intel or "little-endian".
           In Big-endian format the byte order in each double word (4 bytes)
           is swapped except for the Short Stroke (2Ch) and Command (7Ch)
           registers.
        4  (XGA-NI only) MFI_CTRL_ENAB. If set the MFI Control register (index
           6Dh) is enabled. This bit is write only.

21x1h  (R/W):  Video Memory Aperture Control
bit   0-1  MEMWIN_ACCESS.
             0 = disable 64k aperture
             1 = enable 64k aperture at 0A0000h
             2 = enable 64k aperture at 0B0000h

21x4h  (R/W):  Interrupt Enable Register
bit     0  START_BLNK_ENAB. If set an interrupt is issued at the start of the
           Vertical Blanking period.
        1  START_PIC_ENAB. If set an interrupt is issued when the Vertical
           Blanking period ends, i.e.. at the start of the frame.
        2  SPRT_DSPCMP_ENAB. If set an interrupt is issued when the hardware
           sprite has been displayed, i.e.. when the beam passes the lower
           right corner.
        6  ACCESS_REJ_ENAB. If set an interrupt is issued if the XGA Memory
           Registers are written to while an XGA command is active, which can
           corrupt the command.
        7  CMD_DONE_ENAB. If set an interrupt is issued
           whenever a graphics command completes.
Note: These bits control the issuing of IRQ2 interrupts.

21x5h  (R/W):  Interrupt Status Register
bit     0  START_BLNK_STAT. Set when the Vertical Blanking starts.
        1  START_PIC_STAT. Set when the Vertical Blanking ends.
        2  SPRT_DSPCMP_STAT. Set when the beam passes the hardware sprite.
        6  ACCESS_REJ_STAT. Set if the XGA Memory Registers are written to
           while an XGA command is active.
        7  CMD_DONE_STAT. Set whenever an XGA command completes.
Note: These bits are set whenever the specified event occurs and remains set
      until cleared by writing a 1 to the field. The bits are set whether the
      corresponding flag in 21x4h is enabled or not.

21x6h  (R/W):  Virtual Memory Control
bit     0  ENAB_VIRT_LU. If set all XGA addresses are translated through the
           386 Memory Management Unit, if clear all addresses are physical.
        2  USER_SUPER. If set the XGA performs access checking. It also
           generates an I/O exception when this register is written to.
           If clear no access or I/O control is performed.
        6  PROT_VIOL_ENAB. If set the XGA will issue an IRQ2 interrupt when
           a memory protection violation occurs.
        7  PAGE_NP_ENAB. If set the XGA will issue an IRQ2 interrupt when a
           virtual page is accessed which is not in memory.

21x7h  (R/W):  Virtual Memory Interrupt Status Register
bit     6  PROT_VIOL_STAT. Set if a protection violation was found.
        7  PAGE_NP_STAT. Set if a not-present page has been accessed.
Note: The bits are set whether or not the corresponding flag in 21x6h is set.
      The bits are cleared by writing a 1 to the bit, but as this will cause
      a page retry of the failed access, care should be taken.

21x8h  (R/W):  Video Memory Aperture Index.
bit   0-5  MEMWIN_BANK. If in 64k aperture mode, this defines the 64k block
           mapped at 0A0000h or 0B0000h. If in 1MB aperture mode bits 4-5
           defines which 1MB block is mapped at the 1MB aperture. bits 0-3
           should be set to 0.

21x9h  (R/W):  Memory Access Mode
bit   0-2  MEMPIX_SIZE. Defines bits/pixel.
             0 = 1bit, 1 = 2 bits, 2 = 4 bits, 3 = 8 bits, 4 = 16 bits.
        3  MEMPIX_FORMAT. If set the video memory is in Motorola or "Big-
           endian" format.

21xAh  (R/W):  Index Register
bit   0-7  The index for the following access to 21xB.
           21xBh accesses the index register set in 21xAh.
           21xCh-21xFh accesses the index register set in 21xAh + 0-3.
           I.e.. a word read of 210Eh (and thus 210Fh) will read (index+2 &
           index+3).

21xAh index  0  (R/W):  Memory Configuration 0
bit   0-1  VRAM_SERDATA_WID. The width of serial VRAM transfers.
             1 = 16bit, 2 = 32bit.

21xAh index  1  (R/W):  Memory Configuration 1
bit     0  VRAM_RASCAS_EXT. If set extended CAS and RAS cycles are used for
           all cycles except refresh.
        1  VRAM_RAS_PRECH. If set extended RAS precharge time is used
           between consecutive VRAM cycles.
        2  VRAM_REF_EXT. If set extended CAS and RAS cycles are used for
           refresh.

21xAh index  2  (R/W):  Memory Configuration 2
bit     3  VRAM_SER_LEN. If set the VRAM serializer is 512 bits long rather
           than 256 bits.

21xAh index  4  (R):  Auto-Configuration
bit     0  (XGA,XGA-NI) BUS_SIZE. If set the XGA is in a 32bit system (MCA,
           EISA, LocalBus), if clear it is in an ISA slot and no 4MB aperture
           mode.
      0,3  (VESA) BUS_SIZE. 0 = 16bit, 1 = 32 bit, 2 = 8 bit.
      4-5  (VESA) Subsystem Interface Configuration.
                   0 = MCA, 1 = ISA, 3 = EISA.

21xAh index 0Ch (R/W):  State A Data
Note: The XGA state can be saved by suspending the current operation in the
      Control Register, then reading the number of DWORDs from the State A
      Data register specified in the State A Length Memory register, then
      reading the number of DWORDs from the State B Data Register specified in
      the State B Length Memory Register and finally saving the frame buffer.
      To restore the state follow the procedure in reverse order ending with
      enabling the suspended operation in the Control Register.

21xAh index 0Dh (R/W):  State B Data
Note: see State Save/Restore process under 21xAh index 0Ch.

21xAh index 10h  W(R/W): Horizontal Total
bit  0-15  Total number of character clocks in a scanline.
           The number of pixels in a scanline is (value+1)*8

21xAh index 12h  W(R/W): Horizontal Displayed.
bit  0-15  Number of displayed character clocks in a scanline.
           The number of displayed pixels is (value+1)*8

21xAh index 14h  W(R/W): Horizontal Blanking Start.
bit  0-15  The character clock at which blanking starts relative to the start
           of display. The pixel is (value+1)*8

21xAh index 16h  W(R/W): Horizontal Blanking End.
bit  0-15  The character clock at which blanking ends relative to the start
           of display. The pixel is (value+1)*8

21xAh index 18h  W(R/W): Horizontal Sync Start.
bit  0-15  The character clock at which Horizontal Sync starts relative to
           the start of display. In pixels: (value+1)*8

21xAh index 1Ah  W(R/W): Horizontal Sync End.
bit  0-15  The character clock at which Horizontal Sync ends relative to the
           start  of display. In pixels: (value+1)*8

21xAh index 1Ch  (W): Horizontal Sync Position 1.
bit   5-6  SYNC_PULSE_DLY1. Can delay the sync pulses half a character clock
             0 = no change, 2 = delay sync 4 pixels.
Note: This register should be programmed with the same value as index 1Eh.